verilogHDL交通灯设计.doc

交通灯设计第一模块 分频模块把50MHz分成1Hzmodule divider (clk_50MHz, clk_1Hz); input clk_50MHz; output clk_1Hz; reg clk_1Hz; reg 30:0 count; parameter N = 50000000; always ( posedge clk_50MHz) begin if ( count = N/2-1 ) begin clk_1Hz = clk_1Hz + 1b1; count = 0; end else count = count + 1b1; endendmodule第二模块 60进制计数器程序：module counter60 ( clkin, reset, countnum); input clkin, reset; /reset 复位 output 5:0 countnum; reg 5:0 countnum; always ( posedge clkin ) begin if ( !reset ) countnum = 0; else begin if ( countnum = 59 ) /六十进制计数 countnum = 0; else countnum = countnum + 1; end endendmodule第三模块控制器程序：module control ( clk, countin, start_sn, start_ew, redn, reds, rede, redw, greenn, greens, greene, greenw); input clk; input 5:0 countin; /60进制计数器 output start_sn, start_ew;/控制东西、南北方向倒计时控制开关 output redn, reds, rede, redw;/东西南北红灯开关 output greenn, greens, greene, greenw;/东西南北绿灯开关reg start_sn, start_ew; reg redn, reds, rede, redw; reg greenn, greens, greene, greenw; always ( posedge clk ) begin if ( countin = 0) begin start_sn = 1; start_ew = 1 & countin = 24 ) begin start_sn = 0; start_ew = 0; greenn = 0; greens = 0; greene = 1; greenw = 1; redn = 1; reds = 1; rede = 0; redw 24 & countin 30 ) begin start_sn = 0; start_ew = 0; greenn = 0; greens = 0; greene = 0; greenw = 0; redn = 1; reds = 1; rede = 1; redw = 1; end else if ( countin = 30 ) begin start_sn = 0; start_ew 30 & countin = 59) begin start_sn = 0; start_ew = 0; greenn = 1; greens = 1; greene = 0; greenw = 0; redn = 0; reds = 0; rede = 1; redw = 1; end endendmodule 第四模块 位倒计时控制程序：module anticount ( clk_1Hz, start, data1, data10, enable ); input clk_1Hz, start; output enable; output 3:0 data10, data1;/倒计时计数 reg enable; reg 3:0 data10, data1; reg 4:0 count; always ( posedge start or negedge clk_1Hz ) begin if ( start ) enable = 1b1; else if ( count = 0) enable = 1b0; end always ( posedge clk_1Hz ) begin if ( enable ) begin if( count = 0) count = 5b11110; else count = count - 1b1; end else count = 5b00000; end always ( negedge clk_1Hz ) begin if ( enable ) begin data10 = count / 10; data1 = count % 10; end else begin data10 = 4b0000; data1 = 4b0000; end endendmodule第五模块 显示电路程序module display ( clk, enable, datain, discode); input clk, enable; input 3:0 datain; output 6:0 discode; reg 6:0 discode; reg 3:0 code; always ( posedge clk ) begin if ( enable ) code = datain; else code = 4b1111; case (code) 4b0000: discode = 7b0111111; 4b0001: discode = 7b0000110; 4b0010: discode = 7b1011011; 4b0011: discode = 7b1001111; 4b0100: discode = 7b1100110; 4b0101: discode = 7b1101101; 4b0110: discode = 7b1111100; 4b0111: discode = 7b0000111; 4b1000: discode = 7b1111111; 4b1001: discode = 7b1101111; default discode = 7b0000000; endcase endendmodule第六模块 输出部分程序：module out ( clk, datain, a, b, c, d, e, f, g); input clk; input 6:0 datain; output a, b, c, d, e, f, g;/数码管七个管脚 reg a