VHDL的数字频率计实现.doc

5us转换为2slibrary ieee;use ieee.std_logic_1164.all;entity fdiv is port(clk:in std_logic; q:out std_logic);end fdiv;architecture a of fdiv is begin process(clk)variable cnt:integer range 0 to 199999;variable ff: std_logic; begin if clkevent and clk=1 then if cnt199999 then cnt:=cnt+1; else cnt:=0; ff:=not ff; end if; end if;q=ff;end process;end a;20MHz转换成1Hzlibrary ieee;use ieee.std_logic_1164.all;entity fdiv is port(clk:in std_logic; q:out std_logic);end fdiv;architecture a of fdiv is begin process(clk)variable cnt:integer range 0 to 99999;variable ff: std_logic; begin if clkevent and clk=1 then if cnt99999 then cnt:=cnt+1; else cnt:=0; ff:=not ff; end if; end if;q=ff;end process;end a;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter10 is Port ( clk : in STD_LOGIC; clr : in STD_LOGIC; en : in STD_LOGIC; count : out STD_LOGIC_VECTOR (3downto 0); cn_out : out STD_LOGIC);end counter10;architecture Behavioral of counter10 is SIGNAL q:STD_LOGIC_VECTOR (3 downto 0);beginprocess(clk,clr,en) begin if clr=1 then q=0000; elsif clkevent and clk=1 then if en=1 then if q9 then q=q+1; else q=0000; end if; end if; end if;end process;process(q)begin if q=9 then cn_out=1; else cn_out=0; end if;end process;count=q;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity load1 is Port ( load : in STD_LOGIC; din : in STD_LOGIC_VECTOR (23 downto 0); dout : out STD_LOGIC_VECTOR (23 downto 0);end load1;architecture Behavioral of load1 isbegin begin if loadevent and load=1 then doutoutp:=1110010; when0001=outp:=0110000; when0010=outp:=1101101; when0011=outp:=1111001; when0100=outp:=0110011; when0101=outp:=1011011; when0110=outp:=1011111; when0111=outp:=1110000; when1000=outp:=1111111; when1001=outp:=1111011; when others=NULL;end case; a=outp(0); b=outp(1); c=outp(2); d=outp(3); e=outp(4); f=outp(5); gclk,q=fre1); U2:div2clk port map(clk=fre1,count_en=fre_en1,clr=cn_clr1,load=load1); U3:counter10 port map(clk=frein,clr=cn_clrl,en=fre_enl,count=dlatchl(3 downto 0),cn_out=cntoutl(0); U4:counter10 port map(clk=cntoutl(0),clr=cn_clrl,en=fre_enl,count=dlatchl(7 downto 4),cn_out=cntoutl(1); U5:counter10 port map(clk=cntoutl(1),clr=cn_clrl,en=fre_enl,count=dlatchl(11 downto 8),cn_out=cntoutl(2); U6:counter10 port map(clk=cntoutl(2),clr=cn_clrl,en=fre_enl,count=dlatchl(15 downto 12),cn_out=cntoutl(3); U7:counter10 port map(clk=cntoutl(3),clr=cn_clrl,en=fre_enl,count=dlatchl(19 downto 16),cn_out=cntoutl(4); U8:counter10 port map(clk=