大连交通大学coa考试题1.pdfVIP

1 In floating point arithmetic multiplication can divide to 4 steps A Check for zero add exponets multiply significands normalize and round B Fetch instrution indirectly address operand execute instrction and interrupt C process scheduling states creats get ready is running and is blocked D load first operand add second operand check overflow and store result 2 Which the following is not the area that the source and result operands can be stored in A Main or virtual memory B CPU register C I O device D Instruction 3 The advantage of ImmediateAddressing is A limited address range B more memory access C limit value range D no memory access 4 The address is known as a type of date because it is represented by A twos complement B a signed integer C an unsigned integer D a number of hexadecimal 5 In direct addressing mode the operanad is in A the main memory B the register R C the instruction D none 6 In sub cycle CPU fetch the operand s address from memory A indirect B fetch C execute D interrupt 7 Which is not in theALU A shifter B adder C complementer D accumulator 8 Instruction pipeline can improve A processing speed of program B accessing speed of memory C accessing speed of I O D accessing speed of RAID 9 The protocol mesi is alse called A write back policy B write update protocol C write invalidate protocol D write through policy 10 MESI protocol can solve the A problem of cache coherence B problem of memory write bottle nek C communication problem of person computer D volatile problem of DRAM 11 At the end of fetch cycle IR holds A instruction B operand C address of operand D address of instruction 12 There are three kinds of BUS Which does not belong to them A address bus B system bus C data bus D control bus 13 Cache s write back policy means write operation to main memory A as well as to cache B only when the relative cache is replaced C when the difference between cache and main mimory is found D only when using direct mapping 14 A four way set associative chache has 63k words main memory has 256M words and divided 32M blocks line size is words A 4 B 8 C 16 D 32 15 In the following description which is NOT right6 A SRAM is faster than DRAM B DRAM needs periodic charg refreshing circuit C DRAM is slower than Flash D ROM does not require power supplied continuously 16 Which RAID level make use of parallel access technique A RAID0 B RAID2 C RAID4 D RAID6 17 RAID stored information that enable the recovery of data lost due to a disk failure A parity B user data C OS D interrupt 18 The signals of interrupt request and acknowledgement exchange between CPU and requesting I O module The rason of CPU s acknowledgement is A to let the I O module remove request signal B to let CPU get the vector from data bus C bothA B D other aims 19 In DMA the DMA module takes over the operations of data transferring from CPU it means A the DMAmodule can fetch and execute instructions like CPU does B the DMA module can control the bus to transfer data to or from meory using stealing cycle technique C the DMA module and CPU work together co operate to transfer data into or from memory D the DMA module get ready it issues interrupt request signal to CPU for getting interrupt service 20 In twos complement two positive intergers add when does overflow occur A There is a carry B Sign bit of result is 1 C There is a carry and sign bit of result is 0 D Can t determine 21 The 8 bits twos complement 128 is 10000000 its 16 bits twos complement is A 1000 0000 1000 0000B 0000 0000 1000 0000 C 1111 1111 1000 0000D 1000 0000 0000 0000 22 The address of the top of stack is stored in register A PCB ACC SPD BP 23 The REGISTERADDRESSING is very fast but it has A very less value range B very less address space C more memory access D very complex address calculating 24 In instrucion the number of addressed is 2 One address doubles as A a result and the address of next instruction B an operand and a result C an operand and the address of next instruction D two closed operands 25 Abranch instruction performed by CPU is to updatae A MBR to contain the instruction B Program counter to contain the address of next instruction C MAR to contain the address of current instruction D IR to contain the instruction that just fetched from memory 26 In register indirect addressing the effective address of operand is stored in A registerB main memoryC instructionD PC 27 The Memory Address Register of CPU connects to BUS A systemB addressC dataD control 28 TheAccumulator is a n register in 8086 A general purposeB DataC addressD control 29 Which is the worst instruction to limit instruction pipeline A ADDAX XB MOVAX X C RETURND ISZ X 30 In MESI protocol the line in the cache is the same as that in main memory and is not present in other cache which state is the line in A ModifiedB exclusiveC sharedD invalid 31 Which of the following attributes associated with architecture A Control signalsB interfacesC Instruction setD memory technology 32 Which of the following statement is not correct A N bits binary address coding can be 2Nstorage word to identify a word B N bits unsigned binary number can represent a value in the range between 0 to 2N 1 C The length of address is 32 bits so addressing range is 4G D 8086 has 20 bite address bus giving 220 1 address space 33 Computer memory is organized into a hierarchy At the top level are the A registersB cacheC main memoryD external memory 34 On address mapping of cache the data in any block of main memory can be mapped to of cache it is direct mapping A any lineB fixed lineC fixed set any lineD A and B 35 Which is the nonvolatile and permanent storge semiconductor memory A SRAMB CD ROMC FLASHD DRAM 36 In hamming code if syndrome contains one only one 1 it means A the old correct bit is errorB the data is error C more than one errorD nor error 37 In two copies of each stripe on separate disks read from either and write to both A RAID 1B RAID2C RAID 3D RAID4 38 When aprocessor access to the disk physical block it must know that the physical blocks on the disk location of three parameters A side head and trackB side sector and cylinder C cylinder sector and trackD side sector and platter 39 There are three types of the Input Output Techniques Which one is not belong them A Interrupt driven I OB programmed I O C direct I O accessD DMA 40 In DMA when does DMAmodule issue interrupt request signal to CPU A before DMAmodule transfers a block data B after DMAmodule finishes a block data transfer C before DMAmodule seizes to use bus D after DMAmodule ends to size bus 12345678910 DDDCAADACA 11121314151617181920 ABBBCBACBB 21222324252627282930 CCBBBBBADB 31323334353637383940 CDABCAABCB II Answer the following questions 1 Interrupt Processing The CPU save information of current program to stack for resuming it What is the important information 2 In MESI protocol READ MISS initiating in invalid and snooping in modified fill in the following table initiatingsnooping State in beginninginvalidModify action State in end 3 In Displacement Addressing EA A R what is the R register holds In Relative Addressing what is the R register 1 PC PSW 4 分 2 initiatingSnooping BegininvalidModified ActionRead data from Write to memory Endsharedshared 4 分 3 base or displacement PC 4 分 得分15 III A four way set associative main memory has 256M words cache has 4M words and block size is 32 words Please answer the following questions 1 Show the format of main memory addresses 2 Which set of cache is memory location FCB5C6AH mapped to What is the tag 3 Which words of main memory may be mapped to cache set 6E8A and tag value is B5H 1 2 分 Line size Block size 32words 25words Word 5bits 2 3 分 Number of sets 4M 32 lines 4lines set 215sets Set 15bits 3 2 分 Memory size 256Mwords 228words Length of RA 28bits Tag 28 5 15 8 bits 1 分 2 3 分 FCB5C6AH 1111 1100 1011 0101 1100 011 0 1010 is mapping to set 5AE3 tag FC 3 4 分 B56E8A 1011 0101110 1 110 1 000 1 010 0 0000 1011 0101110 1 110 1 000 1 010 1 1111 words of main memory B5 DD140 B5 DD15 Tag 8 itbSet 15 bitWord 5 bit IVAccording to the instruction of the following Answer the questions 1 Show all the micro operations for the following instruction BSAX Branch and save address Address of instruction following BSAis saved in X Execution continues from X 1 2 Which addressing mode is included in this instruction Please draw the figure of its addressing mode 3 According to the initial value of the following figure at the end of Execute cycle what is the value of PC MBU MAR and IR hold Answer 2 4 分 PC 201