FPGA VHDL串口.doc

时钟4分频，freqd_dff.vhd文件clk_in：时钟输入clk_out：时钟输出-library ieee;use ieee.std_logic_1164.all;library altera;use altera.maxplus2.all;entity freqd_dff isgeneric(n: integer :=2);port(clk_in: in std_logic;clk_out: out std_logic);end freqd_dff;architecture freqd_dff_arch of freqd_dff issignal q: std_logic_vector(0 to n);beginq(0) = clk_in;G1: for i in 0 to (n-1) generateUx: dff port map(not q(i+1), q(i), 1, 1, q(i+1);end generate; clk_out = q(n); end freqd_dff_arch;-波特率产生，clock.vhd文件clk:50m时钟clk_out:4倍的波特率时钟sel:波特率选择端，可接拨动开关。00:1200的波特率01:960010:3840011:115200的波特率-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;library altera;use altera.maxplus2.all;entity clock isport(clk: in std_logic;clk_out: out std_logic;sel: in std_logic_vector(1 downto 0);end clock;architecture clock_arch of clock issignal count: std_logic_vector(31 downto 0);constant step96: integer :=3298535;-3298535：9600；constant step11: integer :=39582419;-115200；constant step12: integer :=412317;-1200;constant step38: integer := 13194139;-38400;signal step: integer;beginstep = step12 when sel= 00 else step96 when sel= 01 else step38 when sel= 10 else step11;process( clk )beginif rising_edge(clk) thencount = count + step;end if;end process;clk_out = count(31);end clock_arch;串口接收，recvive.vhd文件clk:4倍的波特率时钟reset:复位端，低电平0复位rx:串口rxrx_done:接收完成，1时完成接收rx_buf:接收的数据-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity recvive isgeneric(framlent:integer:=8);Port(clk, reset: std_logic;rxbuf: out std_logic_vector(7 downto 0);rx: in std_logic;rx_done: out std_logic);end recvive;architecture behave of recvive issignal txen: std_logic;beginrx_done 0);elsif rising_edge(clk) thenif txen = 1 thentxreg(35 downto 1) := txreg(34 downto 0);txreg(0) := rx;end if;end if;rxbuf = txreg(2)&txreg(6)&txreg(10)&txreg(14)&txreg(18)&txreg(22)&txreg(26)&txreg(30);end process;process(clk, reset)variable tcnt: std_logic_vector(5 downto 0); beginif reset=0 thentxen = 0;elsif rising_edge(clk) thenif txen =0 thentxen = not rx;else if tcnt = 100011 thentxen = 0;end if;end if;end if;if reset=0 thentcnt := 000000;elsif rising_edge(clk) thenif txen =1 thentcnt := tcnt + 1;elsetcnt := 000000;end if;end if;end process;end behave;-串口发送，recvive.vhd文件clk:倍的波特率时钟reset:复位端，低电平0复位send：发送信号，高电平开始发送tx:串口txtx_done:发送完成，1时完成发送tx_buf:要发送的数据-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity transferz isgeneric(framlent:integer:=8);Port(clk, reset, send: in std_logic;txbuf: in std_logic_vector(7 downto 0);tx: out std_logic;tx_done: out std_logic);end transferz;architecture behave of transferz issignal txen: std_logic;begintx_done = not txen;process(clk, reset)variable txreg: std_logic_vector(9 downto 0):=1111111111;beginif reset=0 thentxreg := 1111111111;elsif rising_edge(clk) thenif txen = 0 thentxreg(9 downto 2) := txbuf(7 downto 0);txreg(0) := 1;txreg(1) := 0;elsetxreg(8 downto 0) := txreg(9 downto 1);txreg(9) := 1;end if;end if;tx = txreg(0);end process;process(clk, reset)variable tcnt: std_logic_vector(3 downto 0) :=0000; beginif reset=0 thentxen = 0;elsif rising_edge(clk) thenif txen =0 thentxen = send;else if tcnt = 1111 thentxen = 0;end if;end if;end if;if reset=0 thentcnt := 0000;elsif rising_edge(clk) thenif txen =1 thentcnt := tcnt + 1;elsetcnt := 0000;end if;end if;end process;end behave;-总设计图，chuankou.bdfclk:50m的时钟输入。reset:复位端，低电平0复位，接复位按键。send：发送信号，低电平发送接，接复位按