先进芯片封装知识介绍ppt课件.ppt

AdvancedPackagingTech Outline PackageDevelopmentTrend3DPackageWLCSP FlipChipPackage PackageDevelopmentTrend SOFamily QFPFamily BGAFamily PackageDevelopmentTrend CSPFamily MemoryCard SiPModule PackageDevelopmentTrend 3DPackage 3DPackage 3DPackageIntroduction FunctionalIntegration High Low 2ChipStackWirebond 2ChipStackFlipChip Wirebond MultiChipStack PackageonPackage PoP Stacking PS fcCSP SCSP PaperThin PiP PoPQFN StackedDie Topdie Bottomdie FOWmateril Wire TSV TSV ThroughSiliconVia Athrough siliconvia TSV isaverticalelectricalconnection via passingcompletelythroughasiliconwaferordie TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits A3Dpackage SysteminPackage ChipStackMCM etc containstwoormorechips integratedcircuits stackedverticallysothattheyoccupylessspace Inmost3Dpackages thestackedchipsarewiredtogetheralongtheiredges Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra interposer layerbetweenthechips Insomenew3Dpackages through siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips Theresultingpackagehasnoaddedlengthorthickness WireBondingStackedDie What sPoP PoPisPackageonPackageTopandbottompackagesaretestedseparatelybydevicemanufacturerorsubcon PoP PoP PS vfBGA PS etCSP LowLoopWire PinGateMold PackageStacking WaferThinning PoPCoreTechnology PoP Allowsforwarpagereductionbyutilizingfully moldedstructureMorecompatiblewithsubstratethicknessreductionProvidesfinepitchtoppackageinterfacewiththrumoldviaImprovedboardlevelreliabilityLargerdiesize packagesizeratioCompatiblewithflipchip wirebond orstackeddieconfigurationsCosteffectivecomparedtoalternativenextgenerationsolutions Amkor sTMV PoP PoP BallPlacementontopsurface BallPlacementonbottom DieBond Mold UnderFulloptional Laserdrilling Singulation FinalVisualInspection BaseM tl Thermaleffect ProcessFlowofTMVPoP Digital Btmdie Analog Middledie Memory Toppkg PotableDigitalGadgetCellularPhone DigitalStillCamera PotableGameUnit Memorydie Analogdie Digitaldie spacer Epoxy PiP EasysystemintegrationFlexiblememoryconfiguration100 memoryKGDThinnerpackagethanPOPHighIOinterconnectionthanPOPSmallfootprintinCSPformat Ithasstandardballsizeandpitch Constructedwith FilmAdhesivedieattachEpoxypasteforTopPKGAuwirebondingforinterconnectionMoldencapsulation WhyPiP PiP MaterialforHighReliabilityBasedonLowWarpage WaferThinning FineProcessControlTopPackageAttachDieAttachetc OptimizedPackageDesign FlipChip Under fill Topepoxy ISM PiPCoreTechnology PiP Analog WBPIP FCPIP PiP PiP W BPiPandFCPiP WLCSP FlipChipPackage WLCSP WhatisWLCSP WLCSP WaferLevelChipScalePackaging isnotsameastraditionalpackagingmethod dicing packaging testing packagesizeisatleast20 increasedcomparedtodiesize WLCSPispackagingandtestingonwaferbase anddicinglater Sothepackagesizeisexactlysameasbarediesize WLCSPcanmakeultrasmallpackagesize andhighelectricalperformancebecauseoftheshortinterconnection WLCSP WhyWLCSP Smallestpackagesize WLCSPhavethesmallestpackagesizeagainstdiesize Soithaswidelyuseinmobiledevices Highelectricalperformance becauseoftheshortandthicktraceroutinginRDL itgiveshighSIandreducedIRdrop Highthermalperformance sincethereisnoplasticorceramicmoldingcap heatfromdiecaneasilyspreadout Lowcost noneedsubstrate onlyonetimetesting WLCSP sdisadvantageBecauseofthediesizeandpinpitchlimitation IOquantityislimited usuallylessthan50pins BecauseoftheRDL staggerIOisnotallowedforWLCSP RDL RDL RedistributionLayerAredistributionlayer RDL isasetoftracesbuiltuponawafer sactivesurfacetore routethebondpads Thisisdonetoincreasethespacingbetweeneachinterconnection bump WLCSP ProcessFlowofWLCSP WLCSP ProcessFlowofWLCSP FlipChipPackage FCBGA PassiveIntegratedFlipChipBGA PI EHS FCBGA PassiveIntegratedExposedHeatSinkFlipChipBGA PI EHS2 FCBGA PassiveIntegratedExposed2piecesofHeatSinkFlipChipBGA MCM FCBGA Multi Chip ModuleFCBGA PI EHS MP FCBGA PassiveIntegratedExposedHeatSinkMultiPackageFlipChip Bump BumpDevelopment BumpDevelopment BumpDevelopment C4FlipChip What sC4FlipChip C4is ControlledCollapsedChipConnectionChipisconnectedtosubstratebyRDLandBumpBumpmaterialtype solder gold C4FlipChipBGA MainFeaturesBallPitch 0 4mm 1 27mmPackagesize upto55mmx55mmSubstratelayer 4 16LayersBallCount upto2912TargetMarket CPU FPGA Processor Chipset Memory Router Switches andDSPetc MainBenefitsReducedSignalInductanceReducedPower GroundInductanceHigherSignalDensityDieShrink ReducedPackageFootprintHighSpeedandHighthermalsupport C2FlipChip What sC2FlipChip C2is ChipConnectionChipisconnectedto