virtex6 fpga architecture_房文雅

Virtex 6FPGAArchitectureIntroduction 工号 0499房文雅 Virtex 6FPGAIntroduction Virtex 6LXTFPGAGenerallogic serialVirtex 6SXTFPGARichDSPandblockRAM serialVirtex 6HXTFPGAHighestbandwidthserial针对各种需要最高的串行连接能力 多达64个串行收发器 以及可支持高达11 2Gbps带宽的通信应用而优化 NotethatahardprocessorcoreisNOTavailableinanyoftheSpartan 6orVirtex 6devices ArchitecturePowerSavings MoredirectroutingLesscapacitanceLUT6architectureLesspowerthanLUT4GlobalCEsReducesdynamicpowerHardenedIPreducespowerconsumptionversusaLUTimplementation GigabitTransceivers PCIExpress technology EMAC DSP blockRAM FIFO ArchitectureAlignment Virtex 6LXT SXTFPGAHighlights 74Kto760Klogiccells5Mbitsto38MbitsofBlockRAMMemory richarchitectureUpto2 000DSPslicesUpto1 200SelectIO interfacepinsLow latencymemoryandparallelinterfacingUpto366 5 Gbpsserialtransceivers 225 GbpsaggregateserialbandwidthinasingledeviceHardened full featuredPCIExpresstechnology 10 100 1000MbpsEthernetMACsEasy high performanceprotocolsupportthatsavesprogrammablelogicAdvancedpackagingwithsuperiorsignalintegrity Virtex 6FPGALogicFabric Virtex 6FPGAConfigurableLogicBlock CLB EachCLBcontainstwoslicesEachslicecontainsfour6 inputLookupTables 6LUT Slicesimplementlogicfunctions slice L Slicesformemoriesandshiftregisters slice M LUT6implements AllfunctionsofuptosixvariablesTwofunctionsofuptofiveorfewervariableseachShiftregistersupto32stageslongMemoriesof64bitsMultipleconfigurationswithinaslice FPGASliceResources Foursix inputLookUpTables LUT WidemultiplexersCarrychain Thisissupportedonfouroftheeightflip flops Fourflip flop latchesFouradditionalflip flops Thesearethenewflip flopsTheimplementationtools MAP mayaffectthepackingofthedesign WideMultiplexers EachF7MUXcombinestheoutputsoftwoLUTstogether Canimplementanarbitrary7 inputfunction Canimplementan8 1multiplexerTheF8MUXcombinestheoutputsofthetwoF7MUXes Canimplementanarbitrary8 inputfunction Canimplementa16 1multiplexerMUXiscontrolledbytheBX CX DXsliceinputMUXoutputcandriveoutcombinatoriallyortotheflip flop latch CarryChain Carrychaincanimplementfastarithmeticadditionandsubtraction CarryoutispropagatedverticallythroughthefourLUTsinaslice ThecarrychainpropagatesfromoneslicetothesliceinthesamecolumnintheCLBaboveCarrylook ahead Combinatorialcarrylook aheadoverthefourLUTsinaslice Implementsfastercarrycascadingfromslicetoslice SliceFlip FlopsandFlip Flop Latches Eachslicehasfourflip flop latches FF L Canbeconfiguredaseitherflip flopsorlatches TheDinputcancomefromtheO6LUToutput thecarrychain thewidemultiplexer ortheAX BX CX DXsliceinputEachslicealsohasfourflip flops FF DinputcancomefromO5outputortheAX BX CX DXinput Thesedon thaveaccesstothecarrychain widemultiplexers orthesliceinputs OnlytheO5inputisavailableintheSpartan 6FPGAIfanyoftheFF Lareconfiguredaslatches thefourFFsarenotavailable SliceFlip FlopandFlip Flop LatchControl Allflip flopsandflip flop latchessharethesameCLK SR andCEsignals Thisisreferredtoasthe controlset oftheflip flops CEandSRareactivehigh CLKcanbeinvertedatthesliceboundarySet Reset SR signalcanbeconfiguredassynchronousorasynchronous Allfourflip flop latchesareconfiguredthesame Allfourflip flopsareconfiguredthesameSRwillcausetheflip floptobesettothestatespecifiedbytheSRVALattributeFFsintheVirtex 6FPGAhaveanadditionalINITVAL TwoTypesofSlices Everyslicecontainsfourlogic functiongenerators orlook uptables eightstorageelements wide functionmultiplexers andcarrylogic Theseelementsareusedbyallslicestoprovidelogic arithmetic andROMfunctions Inadditiontothis someslicessupporttwoadditionalfunctions storingdatausingdistributedRAMandshiftingdatawith32 bitregisters SlicesthatsupporttheseadditionalfunctionsarecalledSLICEM othersarecalledSLICEL EachCLBcancontainzerooroneSLICEM SLICEM Fullslice LUTcanbeusedforlogicandmemory SRL HaswidemultiplexersandcarrychainSLICEL Logicandarithmeticonly LUTcanonlybeusedforlogic notmemory Haswidemultiplexersandcarrychain SLICEMUsedasDistributedSelectRAM Synchronouswrite asynchronousread Canbeconvertedtosynchronousreadusingtheflip flopsavailableinthesliceVariousconfigurations Singleport OneLUT6 64x1or32x2RAM Cascadableupto256x1RAM Dualport D 1read writeport 1read onlyport Simpledualport SDP 1write onlyport 1read onlyport Quad port Q 1read writeport 3read onlyports Virtex 6FPGABlockRAMandFIFO 600 MHzoperationwhenusingdatapipelineoption Alloperationsaresynchronous alloutputsarelatched Dataoutputhasanoptionalinternalpipelineregister Fasterclockrate butincreasedlatencyTwoindependentportsaddresscommondata Individualaddress clock writeenable clockenable IndependentwidthsforeachportMultipleconfigurationoptions Truedual port simpledual port single portIntegratedcascadelogic Widens deepensFIFOs Creates64kx1fromtwo32kx1blockRAMsByte writeenable Enhancesprocessormemoryinterfacing Virtex 6FPGABlockRAMandFIFOBlock Virtex 6FPGATrueDual PortBlockRAM Truedual portflexibility CanperformreadandwriteoperationssimultaneouslyandindependentlyonportAandportB Eachporthasitsownclock enable writeenable Everywritealsoperformsareadoperation Readbeforewrite writebeforeread ornochange Simultaneousread writeorwrite writetothesamelocationcancausedatacorruption MakesurethataddressandcontrolsignalsarestableduringoperationBRAMconfigurations 32Kx1 16Kx2 8Kx4 4Kx9 2Kx18 1Kx36 Ortwoindependent 16Kx1 8Kx2 4Kx4 2Kx19 1Kx18 Eachportcanhaveitsondepthxwidth ButFIFOalwayshasidenticalreadandwritewidth Virtex 6FPGASimpleDual PortBlockRAM Onereadportandonewriteport NaturalstructureforFIFOsAllowswidestimplementation 72 bitdataononeorboth36Kbports Upto72 bitreadandwriteinoneclockcycle 36 bitwidthfor18KbblockRAM Thisdoublesthememorybandwidthperblock Virtex 6FPGABlockRAMConfigurations Virtex 6FPGABlockRAMisCascadable Built incascadelogicfor64Kx1 Cascadetwoverticallyadjacent32Kx1blockRAMswithoutusingexternalCLBlogicorcompromisingperformance SavesresourcesandimprovesspeedoflargermemoriesCascadeoptionforlargerarrays 128Kb 256Kb 512Kb 1Mb UsingexternalCLBlogicfordepthexpansion NotquiteasfastascascadedblockRAMs WidthexpansionusesparallelblockRAMs BasicI OResources Virtex 6FPGA AllI Osareincolumns 9 30I Obanks dependingonchiptype 40I OsperbankPandNpinscanbeconfiguredas Individualsingle endedsignalsor DifferentialpairTwoblocksoflogicperI Opair Masterandslave CanoperateindependentlyorconcatenatedEachblockcontains IOSERDES Paralleltoserialconverter serializer Serialtoparallelconverter De serializer IODELAY Selectablefine graineddelay SDRandDDRresources Virtex 6FPGAI OTile SelectIOLogicResources Combinatorialinput output3 stateoutputcontrolRegisteredinput outputRegistered3 stateoutputcontrolDouble Data Rate DDR input outputDDRoutput3 statecontrolIODELAYE1providesuserscontrolofanadjustable fine resolutiondelayelementSAME EDGEoutputDDRmodeSAME EDGEandSAME EDGE PIPELINEDinputDDRmode ILOGICResources ILOGICcansupportthefollowingoperations Edge triggeredD typeflip flop IDDRmode OPPOSITE EDGEorSAME EDGEorSAME EDGE PIPELINED Levelsensitivelatch Asynchronous combinatorial CombinatorialInputPath ThecombinatorialinputpathisusedtocreateadirectconnectionfromtheinputdrivertotheFPGAlogic Thispathisusedbysoftwareautomaticallywhen 1 Thereisadirect unregistered connectionfrominputdatatologicresourcesintheFPGAlogic 2 The packI Oregister latchesintoIOBs issettoOFF InputDDROverview IDDR ThereisonlyoneclockinputtotheIDDRprimitive Fallingedgedataisclockedbyalocallyinvertedversionoftheinputclock TheIDDRprimitivesupportsthefollowingmodesofoperation OPPOSITE EDGEmode SAME EDGEmode SAME EDGE PIPELINEDmodeThesemodesareimplementedusingtheDDR CLK EDGEattribute OPPOSITE EDGEMode ThedataispresentedtotheFPGAlogicviatheoutputQ1ontherisingedgeoftheclockandviatheoutputQ2onthefallingedgeoftheclock SAME EDGEMode IntheSAME EDGEmode thedataispresentedintotheFPGAlogiconthesameclockedge However thedatapairtobeseparatedbyoneclockcycle SAME EDGE PIPELINEDMode IntheSAME EDGE PIPELINEDmode thedataispresentedintotheFPGAlogiconthesameclockedge TheoutputpairsQ1andQ2arepresentedtotheFPGAlogicatthesametime Input OutputDelayElement EveryI OblockcontainsaprogrammableabsolutedelayelementcalledIODELAYE1 Itcanbeappliedtothecombinatorialinputpath registeredinputpath combinatorialoutputpath orregisteredoutputpath ItcanalsobeaccesseddirectlyintheFPGAlogic IODELAYE1allowsincomingsignalstobedelayedonanindividualbasis ThetapdelayresolutionisvariedbyselectinganIDELAYCTRLreferenceclockfromtherangespecifiedintheVirtex 6FPGADataSheet TheIODELAYE1resourcecanfunctionasIDELAY ODELAY orbidirectionaldelay OLOGICResources OLOGICconsistsoftwomajorblocks onetoconfiguretheoutputdatapathandtheothertoconfigurethe3 statecontrolpath Thesetwoblockshaveacommonclock CLK butdifferentenablesignals OCEandTCE Bothhaveasynchronousandsynchronoussetandreset SRsignal controlledbyanindependentSRVALattribute Theoutputandthe3 statepathscanbeindependentlyconfiguredinoneofthefollowingmodes EdgetriggeredDtypeflip flop DDRmode SAME EDGEorOPPOSITE EDGE Levelsensitivelatch Asynchronous combinatorial clockingresources Clockmanagementtile CMT TwoPLL basedMixed ModeClockManagers MMCMs ineachClockManagementTile CMT UptonineCMTsperdevice Performsfrequencysynthesis clockde skew andjitter filtering Highinputfrequencyrange 10 800MHz TheVirtex 6FPGAdoesnothaveanyDCMs MMCMabletoimplementbothDCMandPLLfunctionality MMCMFeatures Therearetwokindsofsoftwareprimitives theBASEprimitiveandADVprimitive TheADVprimitivewillgiveyouaccesstotheadvancedfeaturesandallowclockswitchingbetweentwoclockswithoutburningaBUFGorBUFGMUX ClockswitchingallowsyoutoseamlesslyswitchbetweentheCLKINandCLK2withoutresettingtheMMCM AdditionalMMCM ADVfeatures Clockinputswitching Phaseshiftport DynamicReconfigurationPort DRP TheMMCMusesPLLsforallofthesefeatures ItcanreplaceexternalPLLstoloweryoursystemcost MMCMsarelocatedinthecentercolumnofthedevice ThePLLisdesignedtoremoveyourinputclockjitter MMCMInternals Phase frequencydetectorcomparesCLKINwithCLKFB Acceptsupto650 MHzinputs Adjuststhechargepumpoutputvoltagehigherorlower ChargepumpcontrolstheVCOfrequencyManydifferentoutputfrequenciescanbegenerated Fout Fin M D O OneMandoneDvalueperMMCM EachMMCMoutputcanhaveitsownOvalue M 1 64 D 1 80 O 1 128Uptoa1 6 GHzVCOenablesversatilefrequencysynthesis TheO5outputisdisabledwhentheO0outputissettoanon integerdivide TheO6outputisdisabledwhenMissettoanon integerdivide D Programmablecounterdivider PFD Phase frequencydetector CP Chargepump LF Loopfilter VCO VoltageControlledOscillator TheClockingWizardisusedtocustomizetheMMCMresources AdditionalMMCMSignals Complementoutputs O0 O3ofeveryMMCMhavebothtrueandcomplementoutputs Provide180degreephaseshiftLOCKED SignalshowingthattheMMCMhaslockedontotheinputfrequencyCLKINSTOPPED FBSTOPPED StatussignalsindicatingthattheinputorfeedbackclockshavestoppedrunningPWRDWN notshown Disable EnablesignaltotheregulatedsupplyofeachMMCM UnusedMMCMsdrawpowerManypossibleinputstoeachMMCM CCIOfrominnerI Ocolumns Globalclockinputs BUFG GTXclocksMMCMoutputsdrive BUFG BUFHinsameregion Performancepathsto BUFIOandBUFR notshown ClockDeskew UseaBUFGonCLKFBOUTifaprecisephaserelationshipbetweeninputclockandoutputclockisrequired MostflexiblesolutionbutrequirestwoglobalclockbuffersRemovetheBUFGonCLKFBOUTifthereisnoneedforaprecisephaserelationship Frequencysynthesisorjitterfilteringonly DedicatedMMCM to MMCMConnection MMCMSinthesameCMTcanbeconnectedwithouttheneedforaglobalclockbuffer OutputclockwillnotbealignedtoinputclockMoreclockfrequenciescanthusbegenerated DedicatedMMCM to MMCMConnection MMCMsinthesameCMTcanbeconnectedwithouttheneedforaglobalclockbuffer OutputoffirstMMCMconnectedtoCLKINofsecondMMCM BUFGinsertedfromCLKFBOUTtoCLKFBINofthefirstMMCMtoalignoutputclockwithinputclock CLKFBOUToffirstMMCMcanalsodrivelogicMorephase alignedclockfrequenciescanthusbegenerated Example Requirement 33 3 MHzexternaloscillatorcontrols 533 MHzdatabeinggeneratedbyI Ologic BUFIO Largeamountoflogicat66MHz BUFG Smalldesignat54MHz BUFH PhaserelationshipbetweeninputclockandoutputclockisirrelevantSolution MMCMvalues M 16 D 1 O0 9 875 O1 1 O2 8 Generates 54MHzonclkout0O0setto9 875usingfractionalcounter 533MHzonclkout1 66MHzonclkout2 TransmitterOverview TheGTXgigabittransceiversareavailablewiththeVirtex 6LXT SXT andHXTsubfamilies Thesearehigh performancetransceiversthatsupportawiderrangeofprotocolsthantheGTPtransceivers TheGTHgigabittransceiversarethehighestbandwidthtransceiverandareavailablewiththeVirtex 6HXTsubfamily Virtex 6FPGAClockDistribution Eachclockregioncontains12BUFHbuffersthatdrivetheglobalclocknetwork Any12ofthe32BUFGscandrivetheBUFHresourcesineachregion Eachclockregionhassixregionalclocknetworks drivenbytheregionalclockbuffersinthelocalregionoreitheroftheneighboringregions EachclockregionhasuptoeightI OclocknetworksperI Ocolumnintheregion aclockregioncanhaveoneortwoI Ocolumns TherearefourlocalI OclocknetworksperI Obank drivenbytheI Oclockbuffersinthatbank TherearetwoadditionalI Oclocknetworksdrivenfromthebankaboveandtwofromthebankbelowexceptinclockregionsonthetoporbottomofthedevice GlobalClocking Drivenbyeightglobalclockpins Therearealsofourclock capableI OpinsperI Obank Fourdifferentialorsingle ended GlobalclockpinsarenottheonlyclockinputresourceAll32BUFGsresideinthecenterofthedeviceBUFGscanbedrivenby Globalclockinputs Clock capableinputs innerI Ocolumnsonly MMCMoutputs OtherBUFG Interconnect BUFR GTX recoveredclockfromGTX BUFGoutputscandrivetheverticalglobalclockspine HorizontalClocking TwelveBUFHsperclockregionDrivenby MMCMinthesameregion BUFGviaverticalclockspine Clock capableinputsinsamehorizontalrow InterconnectCandrivelogicviahorizontalglobalclocklinesBUFHsonleftandrightofverticalspinecanbedrivenbythesameCCIOorMMCMoutput RegionalClocking UptoeightBUFRsperclockregion FourperI ObankDrivenby Clock capableinputs Interconnect GTX MMCMhigh performanceclocksCandrive Logic IOlogic MMCM BUFG I OClocking Twosingle regionBUFIOsandtwomulti regionBUFIOsineachI Obank TheseI OclockbuffersaredesignedtorouteclockswithinI Ocolumns Thefourclock capableI OpairsineachI ObankareidentifiedbythelettersCCinthepinname ThepinsthatconnecttotheBUFIOsthatcandrivemultipleregionsaredesignatedMRCC Single regionpinsaredesignatedSRCC Drivenby Clock capableinputsinthesameI Obank MMCMoutputsviahigh performancepathsCandrive I OlogicinthesameandadjacentI Obanks DDRandSDRflip flopsintheILOGIC OLOGICblock ISERDESandOSERDESresources BUFIOcandrivelogicresourcesonlyinthesameI OcolumnBecauseofthelowfanout theyhaveextremelylowskew andveryshortinsertiondelay idealforsource synchronousinterfaceapplications Source SynchronousInterfaces I OandregionalclocknetworkscombinedwithISERDES OSERDESprovidepowerfultoolsforcreatingsourcesynchronousinterfacesBUFRissetto NifinterfaceisSDR or N 2 ifDDR Ncanbe2to8inSDR and2to10inDDR Virtex 6FPGADSP48E1Slice TheDSP48E1slicesupportsmanyindependentfunctions Thesefunctionsincludemultiply multiplyaccumulate MACC multiplyadd three inputadd barrelshift wide busmultiplexing magnitudecomparator bit wiselogicfunctions patterndetect andwidecounter ThearchitecturealsosupportscascadingmultipleDSP48E1slicestoformwidemathfunctions DSPfilters andcomplexarithmeticwithouttheuseofgeneralFPGAlogic Virtex 6FPGADSP48E1Slice EachDSP48E1slicehasatwo inputmultiplierfollowedbymultiplexersandathree inputadder subtracter accumulator TheDSP48E1multiplierhasasymmetricinputsandacceptsan18 bittwo scomplementoperandanda25 bittwo scomplementoperand Themultiplierstageproducesa43 bittwo scomplementresultintheformoftwopartialproducts Thesepartialproductsaresign extendedto48bitsintheXmultiplexerandYmultiplexerandfedintothree inputadderforfinalsummation Thisresultsina43 bitmultiplicationoutput whichhasbeensign extendedto48bits Therefore whenthemultiplierisused theaddereffectivelybecomesatwo inputadder Virtex 6FPGADSP48E1Slice A B C CARRYIN CARRYINSEL OPMODE BCIN PCIN ACIN ALUMODE CARRYCASCIN MULTSIGNINalongwiththecorrespondingclockenableinputsandresetinputs arelegacyportsfromtheVirtex 5family TheDandINMODEportsareuniquetotheVirtex 6family WithindependentCport eachDSP48E1sliceiscapableofMultiply Add Multiply Subtract andMultiply Roundoperations ConcatenatedAandBports A B bypassthemultiplierandfeedtheXmultiplexerinput The30 bitAinputportformstheupper30bitsofA Bconcatenateddatapath andthe18 bitBinputportformsthelower18bitsoftheA Bdatapath TheA Bdatapath togetherwiththeCinputport enableseachDSP48E1slicetoimplementafull48 bitadder subtracterprovidedthemultiplierisnotused whichisachievedbysettingUSE MULTtoNONE orDYNAMIC EachDSP48E1slicealsohastwocascadedinputdatapaths ACINandBCIN providingacascadedinputstreambetweenadjacentDSP48E1slices Thecascadedpathis30bitswidefortheAinputand18bitswidefortheBinput ApplicationsbenefitingfromthisfeatureincludeFIRfilters complexmultiplication multi precisionmultiplicationandcomplexMACCs Virtex 6FPGADSP48E1Slice Multiplexersarecontrolledwithdynamiccontrolsignals suchasOPMODE ALUMODE andCARRYINSEL enablingagreatdealofflexibility DesignsusingregistersanddynamicopmodesarebetterequippedtotakeadvantageoftheDSPslice scapabilitiesthancombinatorialmultiplies Ingeneral theDSPslicesupportsbothsequentialandcascadedoperationsduetothedynamicOPMODEandcascadecapabilities FastFourierTransforms FFTs floatingpoint computation multiply add sub divide counters andlargebusmultiplexersaresomeapplicationsoftheDSPslice AdditionalcapabilitiesoftheDSPsliceincludesynchronousresetsandclockenables dualAinputpipelineregisters patterndetection LogicUnitfunctionality singleinstruction multipledata SIMD functionality andMACCandAdd Accextensionto96bits TheDSPslicesupportsconvergentandsymmetricrounding terminalcountdetectionandauto resettingforcounters andoverflow underflowdetectionforsequentialaccumulators SimplifiedDSP48E1SliceOperation ThemathportionoftheDSP48E1sliceconsistsofa25 bitpre adder a25 bitby18 bittwo scomplementmultiplierfollowedbythree48 bitdatapathmultiplexers withoutputsX Y andZ Thisisfollowedbyathree inputadder