SP7715A-2_CS SC8815_SC6815 Design Guide V100

SC8815 SC6815DesignGuideV1 0 0 ReversionHistory 2 Content BaseBandDesignGuide PMUDesignGuide RFDesignGuide SystemDiagram 3 ConnectivityDesignGuide 4 SystemDiagram SystemDiagram 5 6 BaseBandDesignGuide BaseBandSystemcontrol DRAM Flash 7 SC8815 SC6815supportdifferenttypeDRAM PleaseconfigurecorrectHWsettingforselection SC8815 SC6815supportdifferenttypeFlash PleaseconfigurecorrectHWsettingforselectedMCPorEMCP BaseBandSystemcontrol RTC 8 SC8815 SC6815support32K less PleaseconfigurecorrectHWsettingforselectionForSR3500CorSR1019C OPTION3directtoGNDnomatterituseexternal32Kor32K less SR3500C SR1019C SC8815 SC6815 BaseBandSystemcontrol RTC 9 32K less R0203 0ohm R0204 C0211 C0212 X0200 NF External32K R0203 NF C0211 C0212 8 2pF R0204 0ohm X0200 32 768K CL 7pF SR3500C SR1019C SC8815 SC6815 BaseBandSystemcontrol VDDRF0 10 VDDRF0support1 8Vor2 8Vdesign PleaseconfigurecorrectHWsettingforselection ForSR3500CorSR1019C itonlysupport2 8Vdesign soOPTION4shouldconnecttoVBATBKdirectly andVBAT OPTshouldconnecttoVBATtoo SR3500C SR1019Conlysupport2 8VVDDRF0 BaseBandSystemcontrol DRIVER SET 11 DRIVER SET B30 mustconnecttoGNDwitha6 2K 1 ResistorThisResistorisforsettingtheBacklightDriver Vibrator KeypadLEDdriver FlashLEDcurrentsourceonAUXADC soitcannotberemove Clockdesign withGPS 12 Note WithGPS itneed0 5ppmTCXOsupply26MtoSR2351 andneedreserveaclockbuffertoBBCLK26M SINE0 REF2 OUTsupply26MtoBBCLK26M SINE1 Clockdesign withGPS 13 SR3500C SR1019C ATV NFC BB Clockdesign withoutGPSSolution1 14 Note WithoutGPS TCXOcanbedelete REF1 OUTsupply26MtoSR2351andBBCLK26M SINE0 REF2 OUTsupply26MtoBBCLK26M SINE1 Clockdesign withoutGPSSolution1 15 SR3500C SR1019C ATV NFC BB ToSR2351 Clockdesign withoutGPSSolution2 16 Note WithoutGPS TCXOcanbedelete REF1 OUTsupply26MtoSR2351andBBCLK26M SINE0 BBCLK26M SINE1canbeFloating Clockdesign withoutGPSSolution2 17 SR3500C SR1019C ATV NFC BB ToSR2351 Download 18 SC8815 SC6815support2typesofdownloadmode USBDownloadCase1 Detectstrappingpin U1TXD state ThesystemwillenterintoUSBdownloadifU1TXDis 0 andUSBcableisinsertedwhenpowerupCase2 KEYIN0detect ThesystemwillalsoenterintoUSBdownloadifKEYIN0 KEYOUT0ispressedandUSBcableisinsertedwhenpowerupUART1DownloadSoftwarethroughsend7Ecommand andjudgethecommandreturnedfromPCinturn DonotneeddetectstrappingpinstateorwhethertheKCOL0 ROW0ispresseddown I2C 19 SC8815 SC6815integrate5I2Cinterfaces I2C 0 I2C 1 I2C 2 I2C 3 I2C 4I2C0dedicatetocamera andI2C1dedicatedtoCTP3muxtootherIO I2C 2 I2C 3 I2C 4 I2C 2usedforSensorandNFCReserved4 7K NF externalpullupResistoronallusedI2Cisrecommended ExternalInterruptInput 20 EXTINT0andEXTINT1hashardwaredebouncefunctionNoexternalpullupneededasEINTfunction GPIOselection1 2 21 PowerdomainofIOsupplyselection ChooseGPIOwithsuitablepowerdomainofIOsupplyforapplicationForexamplePleasechoosesuitableGPIOforperipheralIC PleasechooseGPIOswithmatcheddirection pull up pull down gpiostateatandafterresetforperipheralICapplicationForexample IOpowerdomainmustbethesameinBBandexternaldevice GPIOselection2 2 22 SC8815 SC6815IOpowerdomaintable 23 EXTRSTNissystemresetinput IthaveinternalpullupresistorandcanbefloatingonSchematicdesign ThePBINT2isforsystemautotesting CustomercanconnectittoIOconnectororreservetestpoint Recommendseries04021KresistorforESDprotection TVSorMLVcanbereserved PBINTMustselectPBINTforthepowerbuttonPBINTsupport7shardwarerebootfunctionPBINT2without7shardwarerebootfunction Keypad1 2 Keypad2 2 KeyfeatureForkeyinsignals therearebuilt in4 7kpull upresistorKeyout0andkeyin0shouldbeusedtoformakeytomakeBBenterUSBdownloadatpowerupAdd510ohmseriesresistoronkeyinandkeyoutforESDprotection 24 UART 25 SC8815 SC6815support3uartports Baudrateupto115 2kbpsuart0anduart2supportHWflowcontrol datarateupto8MbpswithHWflowcontrl U1TXDisastrappingpinforUSBdownloadmodeenablecontrol UART1GenerallyusedforsoftwareD Lport UART0GenerallyusedtocontrolSR2351 Allthe3UARTportscanbeeasilyconnectedtotheUARTportofanexternalIC IIS 26 SC8815 SC6815support2IISports compliantwiththeIIS PCMstandardBothIIS0andIIS1aremuxedforotherfunctionSupportMasterandslave WideselectionofIISdatalengths8 16 32bitsIIScompliantwithPCMPCM CLKsharewithIIS SCKPCM INsharewithIIS SDIPCM OUTsharewithIIS SDOPCM SYNCsharewithIIS LRCK AsaMaster Asaslave SPI 27 SC8815 SC6815support3SPIports Daterateupto24MbpsSupport3 wiremode MasterorslavemodeSerialclockwithprogrammablefrequencySPI2dedicatedwithRGBLCMcontrol Asamaster Asaslave SDIO1 2 28 PowerVDDSD03 0V 250mA PowerforSC8815 SC6815andSDcardVSDpoweredforSDIO0interfaceinBBchip noexternalconnectionneededVSD1ispowerdomainofSDIO1 shouldselectedthecorrectpowerforSDIO1interface SDIO2 2 29 SC8815 SC6815support2SDIO2 0ports CLKfrequenceupto48MhzReserveapull upresistoronCMDfordrivingcapabilityadjust 1 ReservedcaponSDIOsignals keepCbus 40pF 2 TF DETnoexternalpullup downResistorneeded 3 R0100isforclkoptmize closetoBB 4 RouteallSDIOsignalstogetherininnerlayer SD CLKlayoutwithGNDprotectedwellisolatlyisstronglyrecommended 1 2 3 4 SIMinterface1 2 30 SC8815 SC6815contains3SIMinterfaces SIM0 SIM1 SIM2 PowerSIM2IOpowerdomainisVSIM2 IN AD22 ifusedasSIMinterface VSIM2 INshouldconnecttoVDDSIM2 SIMinterface2 2 31 SupportthreeSIMinterfaces SIM0 SIM1 SIM2 ReserveESDprotectioncomponentsforSIM CLK SIM RST SIM DAisrecommended 1 R6400ReservedforNFC 2 OnlySIM0supportTD SCDMASIMclklayoutwithGNDprotectedwellisolatlyisstronglyrecommended 1 1 1 2 LPDDR21 5 SC8815 SC6815LPDDR2signalgroup 32 LPDDR22 5 SC8815 SC6815LPDDR2connectionSupportonly1 2Vdevices ChoosingfromOption2 1 Support16bit 32bitLPDDR2 Supportupto667Mbps 333MHz Supportupto8GbitperCS 33 LPDDR23 5 SchematicItmustpullZQ0tolowwith240ohm 1 andplaceclosetoG3 F3pin R0501canbeNFifLPDDR2onlyhassingledie EMCKE0andEMCKE1canbeconnectedtogether EMCSN0mustconnecttothesignalpath EMCSN1canNC notconnect ifLPDDR2onlyhassingledie 34 LPDDR24 5 VDDMEMPlaceatleast4 7uF 0 1uF 0 01uFcapacitorsclosetoBB sinputPlaceatleast2 0 1uF 2 1uFcapacitorsclosetoLPDDR2 sinput 35 LPDDR2 BB LPDDR25 5 VDD1V8andDDR2 BUFOUTForVDD1V8 Placeatleast1uFcapacitorsclosetoLPDDR2 0 1uFisoptional ForDDR2 BUFOUT Placeatleast0 01uFcapacitorsclosetoLPDDR2 36 Nand eMMCcompatibledesign1 6 Nand eMMCpowerForVDDNF EMMC Placeatleast1uFcapacitorsclosetoNand eMMC 0 1uFisoptionalForVDDNF VDDI Placeatleast1uFcapacitorsclosetoNand eMMCIfuseNand VNFandVNF1connecttoVDD1V8IfuseEMMC VNFconnecttoVDD1V8 VNF1connettoVDDEMMCIO 37 BB Nand EMMC Nand eMMCcompatibledesign2 6 NAND R0506 R0510 0R R0511 0514 NF R0502 10K C0532 NF C0533 NFEMMC R0506 R0510 NF R0511 0514 0R R0502 NF C0532 0 1uF C0533 1uF 38 Nand eMMCcompatibledesign3 6 Nand eMMCPinlistsNANDpinVSEMMCpinNANDandEMMCsharedpin 39 Nand eMMCcompatibledesign4 6 ConnectblackresistorforNANDasshownonthepicture ConnectredresistorforeMMCasshownonthepicture 40 Nand eMMCcompatibledesign5 6 StrappingPinItneedsexternalresistorstoselectmemorytypeanddownloadmode NFD00internalpullup defaulthigh 41 Nand eMMCcompatibledesign6 6 Werecommendthatconnect0ohminseriestoNFD00 NFD02topreventabnormalopretaiononNand EMMCcompatibledesign 42 LCDDesignGuide1 7 43 OverviewInterfaceSupport16 18 and24 bitsDPI eDPIoutput Support8 9 16 18 and24 bitsDBIoutput SupportspanelresolutionuptoFWVGA 854X480 ChipModulePOWERLCMIOpoweratVLCD LCDDesignGuide2 7 44 RGBinterface BBsidePCLKwouldbeprotectedbyGND SPI2alsobeusedwithRGBinterface RGB565D 15 11 R 4 0 D 10 5 G 5 0 D 4 0 B 4 0 RGB666D 17 12 R 5 0 D 11 6 G 5 0 D 5 0 B 5 0 RGB888D 23 16 R 7 0 D 15 8 G 7 0 D 7 0 B 7 0 LCDDesignGuide3 7 45 RGBinterface LCMsidePCLKshouldbeprotectbyGND EMIfiltersorCapsareneededforbetterRFperformance LCDDesignGuide4 7 46 MCUinterface BBsideSupport8 9 16 18 24 bitsDBIinterfaceLCM lowalignment LCDDesignGuide5 7 47 MCUinterface LCMsideEMIfiltersorCapsareneededforbetterRFperformance LCDDesignGuide6 7 48 6LEDs 8LEDs ParallelBacklightDriverSupport4channels Maxsupport8LEDs Sinksuptomax45mAofloadcurrentperchannel Brightnesscanbecontrolledbysoftware onestepis0 625mA IB0mustbeneededwheninternalparallelbacklightisused FortheLEDcurrentmeasurebyIB0 4LEDs LCDDesignGuide7 7 49 SeriesBacklightDriverNointernalSeriesBacklightdriversupport mustuseexternalBLICforseriesLCDGPIOwithPWMfunctionforBrightnesscontrolPayattentiontoratedcurrentofL4100 FB4100 FB4100cannotberemovedforEMIperformance D4100reversevoltage 40VandC4106ratedvoltage 50V CTP1 2 50 COFCTPI2C1hasinternalpullupresistor reserveexternalpullupresistor NF isrecommended 4 Series510ohmResistoronCTPinterfaceforESDprotection 1 ReserverESDcomponents NF onCTPinterface 2 Series1Kohm 100MhzbeadonCTPpowerforRFdisturbancesuppress 3 FormoredetailaboutCTPDesign consultyourCTPICmanufacturer 1 2 3 4 CTP2 2 51 COBCTPI2C1hasinternalpullupresistor recommendreserveexternalpullupresistor 2 C4108ratedvoltageneedhigherthan10V 1 FormoredetailaboutCTPDesign consultyourCTPICmanufacturer 1 2 CameraDesignGuide1 2 POWERVDDCAMDforcorepowersupply maxoutput1 8V Aseries0ohmonVDDCAMDisrecommendedforsomesensormayhaveinternalLDOforSensorcorepowerVDDCAMIOforIOpowersupply maxoutput1 8VCameraanalogpowerneedgoodprotection A2 2uFCapforVDDCAMAareneededatCameraendforgoodphotoqualitySC8815 SC6815integrateFlashlightcontrol Flash CameraDesignGuide2 2 53 Interface8bitsCCIRinterface twocamerasupportSupportJPEGimagesensorsizesupto5MpixelsSupportYUVimagesensorsizesupto2MpixelsEMIfiltersorCapsareneededforbetterRFperformanceMCLK PCLKneedgoodprotectionwithGND USB1 4 54 OverviewTheUSBisusedtodownload calibration finaltestinfactory Whensystempoweron USBwillenterintodownloadmodeifU1TXDispulledtoGNDorkeyin0isshorttokeyout0 TheUSB2 0configurationssupporthigh speed HS 480 Mbps andfull speed FS 12 Mbps transfers butnotsupportOTG Host USB2 4 55 USBPowersupplyLDOVDDUSBisdedicatedforUSBPHYinBBfortypicalUSBapplication USB3 4 56 USB VRES 200ohm 1 resistorforUSBPHYreferencecurrentsource TheVRESresistormustbe200ohmandwith1 precision andshouldbeplacedasclosetoBB AJ21pin aspossibleinPCBlayout USB4 4 57 VCHGTracewidthshouldbemorethan1mm 1 USBdifferentialpairshouldberoutedas90 ohmimpendance 2 ESDprotectioncomponentsforUSBdifferentialpairisrecommended 3 TheequivalentcapacitanceloadingofESDdeviceshouldbelessthan1pf 3 CapC6201isadifferentialcapcrossDPandDM ItisreservedforUSBeyepatterntuningandshouldbenomorethan5 0pF 4 2 1 3 4 ATV NMI601BAA 1 4 58 POWERIfnotneed3simdesign VDDSIM2canbeusedforATVpowersupply andselecttheVSIM2powerdomainGPIOforATVcontrolisrecommendedNMI601BAAhasinternalLDOoutput1 2V noexternal1 2Vsupplyneeded ATV NMI601BAA 2 4 59 CCIRinterfaceSharetheCCIRinterfaceandI2C0withCamera UseCCIRCK1forATVPCLKTheseriesresistoronCCIRinterfaceshouldajusttoreduceinterferencefromCamera ATV BB ATV NMI601BAA 3 4 60 AudioAIL R1canbeusedforATVaudioinputCLKTheSR3500Csupport4channelREF OUT REF3 OUTcanbeusedforATV26Mclksource BB ATV ATV SR3500C ATV NMI601BAA 4 4 61 ANTFormoredetailaboutATVdesign Pleaseconsultyourchipvendor NFC1 5 62 Diagram NFC2 5 63 POWERNFCpoweruseVBAT NFCIOpoweruseVDD1V8SIMpowersupplyshouldchangefromBBVDDSIM0toNFCSIMVCC NFC SIM NFC3 5 64 SchematicdesignPoweroncontrolshouldaddlevelshiftfromBBGPIOtoNFCVENTheSR3500CREF4 OUTcanbeusedforNFC26Mclksource recommendreserve27 12MhzDCXOI2C2hasinternal4 7Kpullupresistor reserveexternal4 7K NF isrecommended BB NFC NFC4 5 65 SchematicdesignDownload pullNFC DL OUThighbeforeNFCreset 1 Normal NFC DL OUTmustbelowatresetandafterreset NFC SWPbaudrateupto1 25Mbitps shoudbeprotectwellwithGNDsheilding 2 Q7601 Q7602 Q7603NMOSarebackupforNFCtest BemountedornotaredetermindedbyNFCtestresult 3 1 2 3 NFC5 5 66 ANTdesignL7600 L7601mustbehighQInductors TVS7600 TVS7601mustbehighvoltageTVS FormoredetailaboutNFCdesign Pleaseconsultyourchipvendor RFSBIandRFCTRL SC8815supportTD GSM SC6815supportGSMSBIforRFtranscievercontrol 1 TD GSMusethesameIQpath IQ0 2 TD GSMusethesameRFCTRL 3 TD GSMAPCOUTforRFTXRAMP 4 67 TXonly TRX 1 2 3 4 ConnectivityControlDesign1 3 68 SPIInterfaceRF SDA RF SCLK RF SCL 32bitsSPI UsedtocontrolWiFi BT FM GPSallfunction exceptWiFiRXthroughputgain AGC0 1 27bitsSPI UsedtocontrolWiFiRXthroughputgain BB SR2351 BB SR2351 ConnectivityControlDesign2 3 69 WiFiAnalogIQInterface 1 WL IP WL IN WL QP WL QNTX RX BTAnalogIQInterface 2 BT IP BT IN BT QP BT QNTX RX FMDigitalIQInterface 3 FM D0 FM D1 2bits RXonly GPSDigitalIQInterface 4 GPS D 1bit BB 1 2 3 4 SR2351 70 ConnectivityControlDesign3 3 WB EN A WB EN BUsedforWiFi BTTRXcontrol BB SR2351 Audio MainMic 71 MICBIAS 2 73V1KohmisreservedforimprovingESDprotect 1 Note Dual MicsolutionneedtonoticetheMicplacement pleaserefertothe 1 Audio AuxMic 72 AUXMICBIAS 2 73V1KohmisreservedforimprovingESDprotect 1 1 Audio MEMSMic 73 SchematicDesign 1 MainMic AUXMic Audio Headphone1 3 74 HEAD MICBIAS 3V1KohmisforESDprotect 1 1 Audio Headphone2 3 75 IntegratedClass G VDDAMP 1 8V 1 ClassGaudioinput C0205andC0213shouldatleast1uFforgoodlowfrequenceperformance 2 1 2 Audio Headphone3 3 76 Designnotice 18ohmand0 22uFareusedtoeliminatehighfrequencenoise 1 Use220Kohmtodecreasepopnoise 2 BeaduseDCRlessthan0 35ohm 3 1 2 3 Audio Speaker1 2 77 IntegratedPASolutionClass Dmode 4 2V 800mWon8OhmloadClass ABmode 4 2V 500mWon8OhmloadBead CapneedusedtogetherordeletetogetherifnoEMIissue 1 1 Audio Speaker2 2 78 ExternalAMPsolution fc 40KHz 1 AMPgainis1 5V V andnoAGC ALCfunction 2 1 2 Audio Receiver 79 SchematicDesign 80 PMUDesignGuide PowerManagement1 6 81 SC8815 SC6815integrate25LDOsand5DCDCconverters 82 PowerManagement2 6 83 PowerManagement3 6 84 PowerManagement4 6 85 PowerManagement5 6 L0300 L0303shouldbeatleast2 2uH lowDCR andRatecurrent 1 2A closetoPoweroutputpin C0301 C0319C0320shouldbeatleast4 7uF closetopowerOutputpin C0321shouldbeatleast10uF closetopowerOutputpin RecommendInductor SPH252012H2R2MT2 2uH 20 DCR 0 096RRatecurrent 1 8Asunlord VDDLDOcanbereplacedwithVBATforcostdown formoredetailaboutit pleasereferto 86 PowerManagement6 6 SC8815 SC6815support3currentSINKmodecontrolFlashSINK 16stepsadjustable 30mA step 20mA 470mAVIBRCurrentsink 16stepsadjustable 10mA step 170mAMAX 0 2mmtracewidthforVIB CTRLKPLEDcurrentsink 16stepsadjustable 5mA step 80mAMAX MOTO Flash KPLED 87 EOS EOSdesignVCHGEOSperformanceimprove donotchangethevalue placeclosetoQ6101 1 D0300andTVS0300 NF forVBATEOSperformanceimprove D0300shouldselect5 1V 500mwdiode placeclosetobaterrycon 2 FormoredetailofEOSdesign pleasereferto 1 1 1 2 88 Powersequence1 2 Power onSequencebyPressingPowerButton 89 Powersequence2 2 Power ontimingparameter Note 1 Typicaltimingparameteriscalculatedbasedonaccurate32 768Kclock 2 Tpwr0 1 3 Tponrdy TpoffrdyandTspoffcouldnotbemeasuredoutsidesincetheyarerelatedtointernalsignals 90 DolphinprovidesanintergratedLi ionbatterychargercontrolmodule WithexternalPNPtransistor NMOSandcurrentsensingresistor DolphincancontrolthechargingofLi ionbattery SC8815 SC6815USBsupportBC1 2standardC6102ratedvoltage 25V R6100 0 068ohm 0805 1 Q6101Pt 1WhREF 100 300 0 5AIc 1A Charger1 2 Mainpath Controlpath ImprovingEOSperformanceDon tchangevalue Currentsensing Routediffirencial BB PutlargecopperforPNPpowerdissipation 91 Charger2 2 ChargingcurrentvsVBATCCchargingcurrentshouldrefertotheselectionofbatteryandexternalchargecomponents recommendmaxchargingcurrentis800mAonSC8815 SC6815 92 CoulombCounter1 2 DolphinintegratesCoulombCounterforprecisecurrentsensingandbatteryvoltagemeasuring Thismodulecontainstwohigh precision ADCs Oneforcurrentsensing whosevoltageprecisionis12 2uV LSB whensampleresistoris20mohm thecurrentprecisionis12 2uV 20mohm 610uA theotherisforbatteryvoltagemeasuringwhoseprecisionis1mV LSB TraceroutingofSENSE PandSENSE Nshouldfollowdifferentialrule 0805 1 93 CoulumbCountingistemprature sensitive sothebatterywithNTCfunctionisamust defult10KNTCresistor ForothervalueNTCresistor thesoftwareneedstobemodified Batteryconnectionasbelow CoulombCounter2 2 BAT TEMP ADCusecurrentsourcemode ThisRESisNF BB 94 RFDesignGuide 95 Introduction SR3500Cisahighlyintegrated single dieradiotransceiverchipthatsupports3GTD SCDMA HSDPA HSUPAandGSM EDGEoperationwithouttheneedforanexternaltransmitSAWfilter balunorLNA ItsupportsSAWLESSoperationforGSMLBandHBRXaswellasTD SCDMAband34and39 Itsupports32K lessdesign 96 Diagram Fig1BlockDiagram TXPort 5 lowband LB highband HB ultrahighband UHB LB1HB1 LB2HB2 HB3 HB4UHB1 UHB2Nooff chipRFSAWFilterRXport 6 SAWLESS 2UHBprimaryports2HBprimaryports2LBprimaryportsReferenceClock BuiltinDCXOFourRefOutput 26MHz 97 Applicationschematic1 5 Fig2Applicationschematic VDD DCXOconnecta1uFcaptoGND noexternalpowersupplyneededSR1019Cpin to pinwithSR3500C ItcanbechangedtoSR1019CdirectlyforGSMonlydesignOnlyTRX1 pinB5 A5 A3 A4 canbeusedasTX RXIQportwhenuseSR1019C SoIQsignalneedselectTRX1forSR3500C SR1019Ccompatibledesign 98 Applicationschematic2 5 Fig3ApplicationschematicwithDCXO 26MHz 10ppmDCXOneeded4channel26MclkREF OUT canbeusedforsystem BT WIFI ATV NFC 99 Applicationschematic3 5 SPI REF OUTREF OUTandSPIinterfaceoperatedat26MHzandneedisolatedfromothersignals especiallyRFtracesandRFcontrolsignals AvoidparallelwithPAramp GSMPAcontrollinesandpowersupplytraces Changetoinnerlayerusingviasandsurroundwithground Fig4Applicationschematic SPI REF OUT 100 Applicationschematic4 5 Fig5Applicationschematicwith32k less 32K lessdesign 101 Applicationschematic5 5 RXSignalConnection TXSignalConnection 102 InterfacebetweenRFandBaseband ThischapterdescribestheinterfacebetweenDolphinT RFandotherkeycomponentssuchasPA andantennaswitch InterfacebetweenSR3500CandDolphinTInterfacebetweenantennaswitchandDolphinTInterfacebetweenDCXOandDolphinT Fig6InterconnectionbetweenSR3500CandDolphinT 103 InterfacebetweenDolphinTandSR3500C TherearethreeinterfacesbetweenDolphinTandSR3500C RXbasebandinputstoDolphinTTXbasebandoutputsfromDolphinTControlsignalsoutputsfromDolphinTTherearetwosetsofSR3500Canalogbasebandinput outputpins oneforTD SCDMAmodeand oranotherforGSM Eachsethastwodifferentialpairs in phaseandquadrature andtheyareconnecteddirectlytoDolphinT Thesetwosetsoffourlinesneedstobetreatedashighlysensitiveanalogdifferentialpairswiththefollowingdesignrecommendations 104 InterfacebetweenDolphinTandSR3500C RouteeachgroupofIQsignalsasdifferentialpairsandkeepadistanceawayfromRFandreferenceclocktraces Avoidcrossingthesetraces ifnecessary crossthe