编码键盘式电子密码锁外文翻译毕业论文.doc

毕业设计文献资料翻译 （原文及译文）原文名称： AT89S51 课题名称： 编码键盘式电子密码锁 14目录一、 原文2二、 译文9AT89S51Features Compatible with MCS-51 Products 4K Bytes of In-System Programmable (ISP) Flash Memory Endurance: 1000 Write/Erase Cycles 4.0V to 5.5V Operating Range Fully Static Operation: 0 Hz to 33 MHz Three-level Program Memory Lock 128 x 8-bit Internal RAM 32 Programmable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Full Duplex UART Serial Channel Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Mode Watchdog Timer Dual Data Pointer Power-off Flag Fast Programming Time Flexible ISP Programming (Byte and Page Mode)DescriptionThe AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4Kbytes of in-system programmable Flash memory. The device is manufactured usingAtmels high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer.By combining a versatile 8-bit CPU with in-system programmable Flash on amonolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a fivevector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. Pin DescriptionVCC Supply voltage.GND Ground.Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups.Port 3 receives some control signals for Flash programming and verification.Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table.RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN Program Store Enable (PSEN) is the read strobe to external program memory.When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2 Output from the inverting oscillator amplifierMemoryOrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.Program Memory If the EA pin is connected to GND, all program fetches are directed to external memory.On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.Data Memory The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.WatchdogTimer(One-time Enabled with Reset-out)The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).When the WDT is enabled, it will increment every machine cycle while the oscillator is running.The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.Using the WDT To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDTat least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written.When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.WDT DuringPower-down and IdleIn Power-down mode the oscillator stops, which means the WDT also stops. While in Powerdown mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode.To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode.Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode,the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode.With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.UART The UART in the AT89S51 operates the same way as the UART in the AT89C51. For further information on the UART operation, refer to the ATMEL Web site ().From the home page, select Products, then 8051-Architecture Flash Microcontroller, thenProduct Overview.Timer 0 and 1 Timer 0 and Timer 1 in the AT89S51 operate the same way as Timer 0 and Timer 1 in the AT89C51. For further information on the timers operation, refer to the ATMEL Web site (). From the home page, select Products, then 8051-Architecture Flash Microcontroller, theProduct Overview.Interrupts The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure 1.Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.Note that Table 4 shows that bit position IE.6 is unimplemented. In the AT89S51,bit position IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products.The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle.论文出处：/dd/docs/datashts/atmel/at89s51_ds.pdf AT89S51主要性能参数：与MCS-51产品指令系统完全兼容4k字节可重擦写Flash闪速存储器4.0V5.5V的工作范围全静态操作：0Hz-33MHz三级加密程序存储器1288字节内部RAM32个可编程I/O口线2个16位定时/计数器6个中断源可编程串行UART通道低功耗空闲和掉电模式 中断恢复掉电模式 看门狗定时器 双数据指针 断电检举 快速编程时间 灵活的ISP编程（字节和页模式）整体描述 该AT89S51是一个低功耗，高性能CMOS 8位微控制器与4000字节的系统内可编程闪存。该设备的生产使用 Atmel的高密度非易失性内存技术，并兼容业界标准80C51指令集和引脚。片上闪存允许程序内存重新编程的系统或通过传统的非易失性存储器编程。 通过结合通用8位中央处理器的系统内可编程闪存的单片芯片， Atmel公司AT89S51是一个功能强大的微控制器提供了一个高度灵活的和具有成本效益的解决办法，许多嵌入式控制应用。 在AT89S51提供以下标准功能：4000字节的Flash ， 128字节的内存， 32个I / O线，看门狗定时器，两个数据指针，两个16位定时器/计数器，一个fivevector两个级别的中断结构，全双工串行接口，片上振荡器，和时钟电路。此外， AT89S51设计的静态逻辑操作到零频率和支持两种软件可选的节电模式。 空闲模式停止的CPU ，同时允许的RAM ，定时器/计数器，串行端口，并中断系统继续运作。在掉电模式保存RAM的内容但冻结振荡器，停用所有其他芯片的功能，直到下一个外部中断或硬件复位。引脚描述 虚拟通道 连接电源电压。 接地 地面。 端口0 端口0是一个8位漏极开路双向I / O端口。作为一个输出端口，每个引脚可以汇8对焦TTL投入。当1秒写入端口0引脚，该引脚可作为高阻抗投入。 端口0也可以配置为复低阶地址/数据总线在访问外部程序和数据存储器。在这种模式下， P0了内部仰卧起坐。 端口还收到0字节的代码在Flash编程和产出代码字节在计划的核查。外部仰卧起坐需要在计划的核查。 端口1 端口1是一个8位双向I / O端口内部仰卧起坐。端口1输出缓冲器可以汇/源四的TTL投入。当1秒写入端口1引脚，他们的退出高内部仰卧起坐，可作为投入。作为投入，端口1引脚的外部正拉低将电源电流（ IIL ）由于内部仰卧起坐。港1还收到低字节为了解决在Flash编程和核查。端口2 端口2是一个8位双向I / O端口内部仰卧起坐。端口2输出缓冲器可以汇/源四的TTL投入。当1秒写入港2针，他们的退出高内部仰卧起坐，可作为投入。作为投入，端口2引脚的外部正拉低将电源电流（ IIL ）由于内部仰卧起坐。 端口2排放高阶地址字节在获取来自外部程序存储器和在访问外部数据存储器，使用16位地址（ MOVX DPTR ） 。在这申请时，端口2使用强大的内部仰卧起坐时，发射谱。在访问外部数据存储器，使用8位地址（ MOVX 里） ，端口2排放的内容特别的P2功能寄存器。 端口2还收到高阶地址位和一些控制信号在Flash编程和核查。 端口3 端口3是一个8位双向I / O端口内部仰卧起坐。端口3输出缓冲器可以汇/源四的TTL投入。当1秒写入端口3引脚，他们的退出高内部仰卧起坐，可作为投入。作为投入，端口3引脚的外部正拉低将电源电流（ IIL ）因为仰卧起坐。 端口3获得某种程度的控制信号的Flash编程和核查。 端口3兼任的职能很多。复位 复位输入 高98振荡器在此引脚两个机器周期，而振荡器运行重置设备。此PIN驱动器高98振荡器期后看门狗超时。该DISRTO位在社会主义AUXR（地址8EH ）可以用来禁用此功能。在默认状态比特DISRTO ，重高的功能已启用。 进修/编程地址锁存器启用（进修）是一个输出脉冲的闭锁低字节的地址在访问外部存储器。该号码也计划脉冲输入（孕酮）在闪光编程。 在正常操作时，进修排放在一个不变的1 / 6振荡器频率和可能用于外部定时或计时的目的。但是请注意，一个进修脉跳过在每个访问外部数据存储器。如果需要，进修业务可以禁用设置位0的SFR的位置8EH 。同位设置，进修积极只有在MOVX或MOVC指令。否则，脚弱退出高的。设置亚历山大禁用位没有任何影响，如果是在外部微控制器执行模式。PSEN计划商店启用（ PSEN ）是阅读选外部程序存储器。 当AT89S51正在执行的代码从外部程序存储器， PSEN被激活每个机器周期两次，但两次都跳过激活PSEN在每个接入外部数据存储器。电子艺界/ VPP外部访问启用。电子艺界必须绑至GND ，以便使该装置撷取代码从外部程序存储器的地点开始，0000H行动FFFFH 。但是请注意，如果锁定位1的设计， EA将在内部锁存复位。电子艺界应绑到VCC内部程序处决。该号码也收到12伏编程使电压（ VPP ）在闪光编程。 XTAL1 输入振荡器的反相放大器和投入运营的内部时钟电路。 XTAL2 输出振荡器的反相放大器内存 组织 MCS - 51单片机的设备有一个单独的地址空间的程序和数据存储器。高达64K的每个字节的外部程序和数据存储器可以得到解决。 程式记忆体，如果以EA引脚连接到GND ，获取所有程序都是针对外部存储器。 关于AT89S51 ，如果电子艺界连接到VCC ，计划获取地址0000H通过FFFH是针对内部存储器和存取的地址1000H是通过FFFFH针对外部存储器。数据存储器的AT89S51实现128字节的片上RAM 。 128字节都可以通过直接和间接寻址模式。栈操作的例子间接寻址，因此，128字节的数据RAM可作为堆栈空间。 看门狗 定时器 （一次性 启用 复位输出） 该定时器是作为恢复方法的情况下的CPU可能会受到软件冷门。该定时器由一个14位计数器和看门狗定时器复位（ WDTRST ） SFR公司。该定时器是拖欠禁用从朝重置。为了使定时器，一个用户必须写入01EH和0E1H依次向WDTRST寄存器（ SFR的位置0A6H ） 。 当定时器已启用，它会增加，而每个机器周期振荡器正在运行。该定时器超时时间依赖于外部时钟频率。没有什么方法可以禁用除了通过的定时器复位（或硬件复位或定时器溢出复位） 。何时定时器溢出，它将驱动器的输出复位高脉冲的复位引脚。 使用定时器为了使定时器，用户必须写入01EH和0E1H顺序登记的WDTRST（ SFR的位置0A6H ） 。当定时器被激活，用户需要的服务以书面01EH和0E1H到WDTRST以避免定时器溢出。 14位计数器溢出到达 16383 （ 3FFFH ） ，这将重置该设备。当定时器已启用，这将增加每个机器周期，而振荡器正在运行。这意味着用户必须重置定时器至少每16383机器周期。重置定时器用户必须写入01EH和0E1H以WDTRST 。 WDTRST是一个只写寄存器。该定时器计数器无法读取或写入。 当定时器溢出，它会产生一个输出复位脉冲的复位引脚。重置脉冲持续时间是98xTOSC ，其中TOSC = 1/FOSC 。以最佳方式利用的定时器，它应该在这些服务的部分代码，将定期被处决的时间内需要以防止定时器复位。 定时器在电源关闭和闲置 在掉电模式振荡器停止，这意味着定时器也会停止。虽然在Powerdown模式下，用户并不需要提供服务的定时器。方法有两种退出掉电模式：由硬件复位或通过一级激活外部中断，这是启用之前进入掉电模式。当电源式是退出硬件复位，服务定时器应该发生，因为它通常不每当AT89S51重置。退出断电中断是一个很大的不同。中断是低了足够长的时间为振荡器稳定。如果中断是使高，中断提供服务。为了防止从设的定时器的装置而中断引脚举行低，定时器不开始，直到中断被拉高。有人建议，定时器复位中断期间服务中断用来退出掉电模式。 为了确保定时器不会溢出的少数几个国家的退出功率下降，这是最好的重置定时器刚刚进入掉电模式。 在进入空闲模式，在该WDIDLE位的SFR AUXR是用来确定是否该定时器继续计数如果启用。计数的定时器保持在闲置（ WDIDLE位= 0 ）作为默认的状态。为了防止定时器从重置AT89S51 ，而在空闲模式，用户应始终成立一个计时器，将定期退出闲置，服务的定时器，并重新空闲模式。与WDIDLE位启用，定时器将停止指望在空闲模式和简历伯爵 离开时从闲置。UART接口的异步运行在AT89S51同样的方式，在AT89C51单片机的UART 。为进一步关于异步操作，指的是Atmel公司的网站（ ）。 从主页，选择产品 ，然后8051架构闪存微控制器 产品概况。定时器0和定时器1 定时器0和定时器1在AT89S51操作一样定时器0和定时器1 AT89C51的。如需进一步信息的定时器操作，指的是Atmel公司的网站（ ） 。从主页，选择产品 ，然后8051建筑闪光微控制器 ，然后产品 中断AT89S51共有5个中断向量：两个外部中断（ INT0和INT1 ） ， 2 定时器中断（定时器0和1 ） ，和串口中断。 所有这些中断源可以单独启用或禁用通过设置或清除位在特殊功能寄存器IE浏览器。 IE浏览器还包含一个全球禁用位，电子艺界，这禁用所有 中断一次。 请注意，表4显示出，一些立场IE.6是执行。在AT89S51 ，位的位置IE.5也没有得到执行。用户软件不应该写谱这些位的职位，因为它们可用于在未来AT89产品。 定时器0和定时器1旗帜， TF0和TF1电视台，分别为S5P2周期中，计时器溢出。的价值观，然后调查的电路中的下一个周期。袄芈蒇袇螀芇蕿蚀聿芆艿蒃肅芅蒁螈羁芄薃薁袆芃芃螆螂芃莅蕿肁节蒈螅羇莁薀薈袃莀艿螃蝿荿莂薆膈莈薄袁肄莇蚆蚄羀莇莆袀袆羃蒈蚂螂羂薁袈肀肁芀蚁羆肁莃袆袂肀薅虿袈聿蚇蒂膇肈莇螇肃肇葿薀罿肆薂螆袅肅芁薈螁膅莃螄聿膄蒆薇羅膃蚈螂羁膂莈蚅袇膁蒀袀螃膀薂蚃肂腿节衿羈腿莄蚂袄芈蒇袇螀芇蕿蚀聿芆艿蒃肅芅蒁螈羁芄薃薁袆芃芃螆螂芃莅蕿肁节蒈螅羇莁薀薈袃莀艿螃蝿荿莂薆膈莈薄袁肄莇蚆蚄羀莇莆袀袆羃蒈蚂螂羂薁袈肀肁芀蚁羆肁莃袆袂肀薅虿袈聿蚇蒂膇肈莇螇肃肇葿薀罿肆薂螆袅肅芁薈螁膅莃螄聿膄蒆薇羅膃蚈螂羁膂莈蚅袇膁蒀袀螃膀薂蚃肂腿节衿羈腿莄蚂袄芈蒇袇螀芇蕿蚀聿芆艿蒃肅芅蒁螈羁芄薃薁袆芃芃螆螂芃莅蕿肁节蒈螅羇莁薀薈袃莀艿螃蝿荿莂薆膈莈薄袁肄莇蚆蚄羀莇莆袀袆羃蒈蚂螂羂薁袈肀肁芀蚁羆肁莃袆袂肀薅虿袈聿蚇蒂膇肈莇螇肃肇葿薀罿肆薂螆袅肅芁薈螁膅莃螄聿膄蒆薇羅膃蚈螂羁膂莈蚅袇膁蒀袀螃膀薂蚃肂腿节衿羈腿莄蚂袄芈蒇袇螀芇蕿蚀聿芆艿蒃肅芅蒁螈羁芄薃薁袆芃芃螆螂芃莅蕿肁节蒈螅羇莁薀薈袃莀艿螃蝿荿莂薆膈莈薄袁肄莇蚆蚄羀莇莆袀袆羃蒈蚂螂羂薁袈肀肁芀蚁羆肁莃袆袂肀薅虿袈聿蚇蒂膇肈莇螇肃肇葿薀罿肆薂螆袅肅芁薈螁膅莃螄聿膄蒆薇羅膃蚈螂羁膂莈蚅袇膁蒀袀螃膀薂蚃肂腿节衿羈腿莄蚂袄芈蒇袇螀芇蕿蚀聿芆艿蒃肅芅蒁螈羁芄薃薁袆芃芃螆螂芃莅蕿肁节蒈螅羇莁薀薈袃莀艿螃蝿荿莂薆膈莈薄袁肄莇蚆蚄羀莇莆袀袆羃蒈蚂螂羂薁袈肀肁芀蚁羆肁莃袆袂肀薅虿袈聿蚇蒂膇肈莇螇肃肇葿薀罿肆薂螆袅肅芁薈螁膅莃螄聿膄蒆薇羅膃蚈螂羁膂莈蚅袇膁蒀袀螃膀薂蚃肂腿节衿羈腿莄蚂袄芈蒇袇螀芇蕿蚀聿芆艿蒃肅芅蒁螈羁芄薃薁袆芃芃螆螂芃莅蕿肁节蒈螅羇莁薀薈袃莀艿螃蝿荿莂薆膈莈薄袁肄莇蚆蚄羀莇莆袀袆羃蒈蚂螂羂薁袈肀肁芀蚁羆肁莃袆袂肀薅虿袈聿蚇蒂膇肈莇螇肃肇葿薀罿肆薂螆袅肅芁薈螁膅莃螄聿膄蒆薇袁节膅薂羄肅蒃薁蚃芀荿薀螆肃芅蕿袈芈膁蚈羀肁蒀蚇蚀袄莆蚇螂肀莂蚆羅袂芈蚅蚄膈膄蚄螇羁蒂蚃衿膆莈蚂羁罿芄螁蚁膄膀螁螃羇葿螀袅膃蒅蝿肈羆莁螈螇芁芇莄袀肄膃莄羂艿蒂莃蚂肂莈蒂螄芈芄蒁袆肀膀蒀罿袃薈葿螈聿蒄葿袁羁莀蒈羃膇芆蒇蚃羀膂蒆螅膅蒁薅袇羈莇薄罿膄芃薃虿羆艿薃袁节膅薂羄肅蒃薁蚃芀荿薀螆肃芅蕿袈芈膁蚈羀肁蒀蚇蚀袄莆蚇螂肀莂蚆羅袂芈蚅蚄膈膄蚄螇羁蒂蚃衿膆莈蚂羁罿芄螁蚁膄膀螁螃羇葿螀袅膃蒅蝿肈羆莁螈螇芁芇莄袀肄膃莄羂艿蒂莃蚂肂莈蒂螄芈芄蒁袆肀膀蒀罿袃薈葿螈聿蒄葿袁羁莀蒈羃膇芆蒇蚃羀膂蒆螅膅蒁薅袇羈莇薄罿膄芃薃虿羆艿薃袁节膅薂羄肅蒃薁蚃芀荿薀螆肃芅蕿袈芈膁蚈羀肁蒀蚇蚀袄莆蚇螂肀莂蚆羅袂芈蚅蚄膈膄蚄螇羁蒂蚃衿膆莈蚂羁罿芄螁蚁膄膀螁螃羇葿螀袅膃蒅蝿肈羆莁螈螇芁芇莄袀肄膃莄羂艿蒂莃蚂肂莈蒂螄芈芄蒁袆肀膀蒀罿袃薈葿螈聿蒄葿袁羁莀蒈羃膇芆蒇蚃羀膂蒆螅膅蒁薅袇羈莇薄罿膄芃薃虿羆艿薃袁节膅薂羄肅蒃薁蚃芀荿薀螆肃芅蕿袈芈膁蚈羀肁蒀蚇蚀袄莆蚇螂肀莂蚆羅袂芈蚅蚄膈膄蚄螇羁蒂蚃衿膆莈蚂羁罿芄螁蚁膄膀螁螃羇葿螀袅膃蒅蝿肈羆莁螈螇芁芇莄袀肄膃莄羂艿蒂莃蚂肂莈蒂螄芈芄蒁袆肀膀蒀罿袃薈葿螈聿蒄葿袁羁莀蒈羃膇芆蒇蚃羀膂蒆螅膅蒁薅袇羈莇薄罿膄芃薃虿羆艿薃袁节膅薂羄肅蒃薁蚃芀荿薀螆肃芅蕿袈芈膁蚈羀肁蒀蚇蚀袄莆蚇螂肀莂蚆羅袂芈蚅蚄膈膄蚄螇羁蒂蚃衿膆莈蚂羁罿芄螁蚁膄膀螁螃羇葿螀袅膃蒅蝿肈羆莁螈螇芁芇莄袀肄膃莄羂艿蒂莃蚂肂莈蒂螄芈芄蒁袆肀膀蒀罿袃薈葿螈聿蒄葿袁羁莀蒈羃膇芆蒇蚃羀膂蒆螅膅蒁薅袇羈莇薄罿膄芃薃虿羆艿薃袁节膅薂羄肅蒃薁蚃芀荿薀螆肃芅蕿袈芈膁蚈羀肁蒀蚇蚀袄莆蚇螂肀莂蚆羅袂芈蚅蚄膈膄蚄螇羁蒂蚃衿膆莈蚂羁罿芄螁蚁膄膀螁螃羇葿螀袅膃螈聿蒄葿袁羁莀蒈羃膇芆蒇蚃羀膂蒆螅膅蒁薅袇羈莇薄罿膄芃薃虿羆艿薃袁节膅薂羄肅蒃薁蚃芀荿薀螆肃芅蕿袈芈膁蚈羀肁蒀蚇蚀袄莆蚇螂肀莂蚆羅袂芈蚅蚄膈膄蚄螈螇芁芇莄袀肄膃莄羂艿蒂莃蚂肂莈蒂螄芈芄蒁袆肀膀蒀罿袃薈葿螈聿蒄葿袁羁莀蒈羃膇芆蒇蚃羀膂蒆螅膅蒁薅袇羈莇薄罿膄芃薃虿羆艿薃袁节膅薂羄肅蒃薁蚃芀荿薀螆肃芅蕿袈芈膁蚈羀肁蒀蚇蚀袄