基于Verilog 的几种边沿探测方法的比较.doc

方法一：buf 缓冲检测法：该方法需要延迟2个clk时钟。timescale 1ns/1psmodule rising_edge_check(clock, signal, rising_flag); input clock; input signal;/input signal output rising_flag;/rising edge flag reg 2:0 temp=3b000;always (posedge clock) temp=temp1:0,signal; assign rising_flag=(temp1:0=2b01)?1b1:1b0;Endmoduletimescale 1ns/1psmodule falling_edge_check(clock, signal, falling_flag); input clock; input signal; output falling_flag;reg 2:0 temp=3b111;always (posedge clock) temp=temp1:0,signal; assign falling_flag=(temp1:0=2b10)?1b1:1b0;endmodule边沿检测仿真波形：双边沿检测：timescale 1ns/1psmodule double_edge_detect( clk, rst_n, data_in, raising_edge_detected, /上升沿检测 falling_edge_detected, /下降沿检测 double_edge_detected /双边沿检测 ); input clk; input rst_n; input data_in; output raising_edge_detected;output falling_edge_detected;output double_edge_detected; wire raising_edge_detected;wire falling_edge_detected;wire double_edge_detected; reg data_in_d1; /定义中间变量1reg data_in_d2; /定义中间变量2always (posedge clk or negedge rst_n)begin if (rst_n = 1b0) begin data_in_d1 = 1b0; data_in_d2 = 1b0; end else begin data_in_d1 = data_in; data_in_d2 = data_in_d1; endend assign raising_edge_detected = data_in_d1 & data_in_d2; / 上升沿检测输出assign falling_edge_detected = data_in_d1 & data_in_d2; /下降沿检测输出assign double_edge_detected = data_in_d1 data_in_d2; /双边沿检测输出Endmodule仿真波形：其中红色为双边沿检测仿真波形：方法2：脉冲采用法：timescale 1ns/1psmodule pluse_edge_dected(clk, reset, clken8M, irq, pps_in, posedge_flag, negedge_flag ); input reset, clk, clken8M; input pps_in; output irq; output posedge_flag; output negedge_flag; reg irq; reg 7 : 0 lpps; reg posedge_flag; reg negedge_flag; /首先用pps_in对低电平脉冲进行八级采样，防止亚稳态传播，增加抗干扰能力 always (posedge clk or posedge reset) begin if(reset) begin lpps = 8h00; end else begin if(clken8M) begin lpps7 : 1 = lpps6 : 0; lpps0 = pps_in;end end end /当检测到上升沿时，触发计数器进行计数。 reg 19 : 0 plus_width_cnt; always (posedge clk or posedge reset) begin if(reset) begin plus_width_cnt = 20b0; irq = 1b0; posedge_flag= 1b0; negedge_flag= 1b0; end else begin irq = 1b0; posedge_flag= 1b0; negedge_flag= 1b0; if(clken8M) begin if(plus_width_cnt != 20hfffff) plus_width_cnt = plus_width_cnt + 20b1; if(lpps = 8b0000_1111) begin/ pps_in posedge judge plus_width_cnt = 20h0000;