外文文献翻译(王德林)0626改.doc

P89LPC9521. 概述P89LPC952 是一款单片封装的微控制器，含有多种低成本的封装形式。它采用了高性能的处理器结构，指令执行时间只需2 到4 个时钟周期。6 倍于标准80C51 器件。P89LPC952集成了许多系统级的功能，这样可大大减少元件的数目和电路板面积并降低系统的成本。2. 特性2.1 主要特性 8KB 可擦除Flash 程序存储器，具有1KB 扇区和64 字节页。单字节擦除特性使得任何字节都可用于非易失性数据存储。 256 字节 RAM 数据存储器和256 字节附加片内RAM。 具有window 比较器的8 输入多路10 位A/D 转换器，结果在允许范围以内或以外都可产生中断。2 个模拟比较器可选择输入和参考源。 2 个16 位定时/计数器（每一个定时器均可设置为溢出时触发相应端口输出或作为PWM 输出），23 位的系统定时器可用作实时时钟（RTC）。 两个增强型UART，具有波特率发生器、间隔检测、帧错误检测和自动地址检测功能。400kHz 字节宽度的I2C 通信端口和SPI 通信端口。 片内高精度的RC 振荡器选项带有时钟倍频器，无需外接振荡器件。可选择RC 振荡器选项并且其频率可进行很好的调节。内部RC 振荡器和任何振荡器源之间的快速切换，提供低功耗有效模式的最佳支持，可快速转变为最高性能。 VDD 操作电压范围为2.43.6V。I/O 口可承受5V（可上拉或驱动到5.5V）。 44 脚封装，使用片内振荡器和复位选项时，至少可获得40 个I/O 口。 P5 的所有管脚可吸收/消耗高电流（20mA）。其它所有的端口管脚都有高消耗电流的能力（20mA）。整个芯片指定了最大值的限制。 看门狗定时器具有独立的片内振荡器，无需外接元件。看门狗预分频器可从8 个值中选择。2.2 其它特性 当操作频率为18MHz 时，除乘法和除法指令外，高速80C51 CPU 的指令执行时间为111222ns。同一时钟频率下，其速度为标准80C51 器件的6 倍。只需要较低的时钟频率即可达到同样的性能，这样无疑降低了功耗和EMI。 串行Flash 在电路编程（ICP）可通过商用EPROM 编程器实现简单的编程。Flash保密位可防止程序被读出。 串行Flash 在系统编程（ISP）可实现已固定在最终应用上的器件的编程。 Flash 程序存储器可实现在应用中编程（IAP）。这允许在程序运行时改变代码。 低电压（掉电）检测可在电源故障时使系统安全关闭。该功能也可配置为一个中断。 空闲和两种不同的掉电节电模式。提供从掉电模式中唤醒功能（低电平中断输入唤醒）。典型的掉电电流为1A（比较器关闭时的完全掉电状态）。 低电平复位输入可由任何内部复位驱动。使用片内上电复位时不需要外接元件。复位计数器和复位干扰抑制电路可防止虚假和不完全的复位。另外还提供软件复位功能。 当选择片内复位时，P89LPC952 只需连接电源和地。 可配置的片内振荡器，其频率可通过用户可编程Flash 配置位进行选择。RC 振荡器选项支持的频率范围为20kHz18MHz。 振荡器失效检测。看门狗定时器具有独立的片内振荡器，因此它可用于振荡器的失效检测。 可编程I/O 口输出模式：准双向口，开漏输出，推挽和仅为输入功能。 端口“输入模式匹配”检测。当P0 口管脚的值与一个可编程的模式匹配或者不匹配时，可产生一个中断。 可控制口线输出斜率以降低EMI，输出最小跳变时间约为10ns。 4 个中断优先级。 8 个键盘中断输入，另加2 路外部中断输入。 施密特触发端口输入。 双数据指针（DPTR）。 扩展的温度范围。 仿真支持。P89LPC952 Flash 存储器1.概述P89LPC952 Flash 存储器提供电路中的电擦除和编程。Flash 可以字节为单位擦除、读取或写入。扇区和页擦除功能可擦除任意的Flash 扇区(1kB)或页(64 字节)。芯片擦除功能可实现整个程序存储器的擦除。ICP 功能通过标准商用编程器来实现。另外，IAP 和字节擦除功能允许程序存储器用作非易失性数据存储器。片内产生的擦除和写入时序为用户提供了友好的编程接口。P89LPC952 Flash 存储器甚至在经过100, 000 次擦除和编程周期后仍然能可靠地保存存储器的内容。存储单元的设计优化了擦除和编程机制。P89LPC952 使用VDD 电压来执行编程和擦除算法。2.特性可在整个操作电压范围内执行编程和擦除。字节擦除允许程序存储器用于存储数据。使用ISP/IAP/ICP 进行读/编程/擦除。内部固化的引导ROM，包含了可用于用户程序的低级IAP 子程序。默认的装载程序可通过串口进行ISP 编程。该程序位于用户程序存储器空间的顶端。Boot 向量允许用户将Flash 装载代码放入Flash 存储器内的任何位置。这种配置为用户提供了应用的灵活性。任意Flash 编程/擦除时间小于2ms。使用工业标准的商用编程器进行编程。可对每一个Flash 扇区进行编程加密。每个字节至少可执行100,000 次擦除/编程。数据至少可保存10 年。3.Flash 的结构P89LPC952 器件包含8 个1KB 扇区的Flash 程序存储器。每个扇区可进一步分成64 字节的页。除了扇区擦除、页擦除和字节擦除外，还包含一个64 字节的页寄存器，它可实现给定页1 到64 字节的同时编程，这彻底降低了整个编程的时间。4. Flash 用作数据存储器P89LPC952 的Flash 程序存储器支持单个字节的擦除和编程。程序存储器的任何一个字节都可通过MOVC 指令来读取，只要包含该字节的扇区未加密（MOVC 指令不能读取加密扇区的程序存储器的内容）。因此，非加密扇区的任何字节都可用来存储非易失性数据。5. Flash 的编程和擦除有4 种方法可实现对Flash 的编程或擦除。第一，在应用固件的控制下，在最终用户应用程序中（IAP）对Flash 进行编程或擦除。第二，使用ICP 功能。通过系统提供的串行时钟/串行数据接口来实现ICP 编程。第三，出厂时，器件的用户代码空间的高512 字节包含一个串行ISP 程序，调用该程序通过串口来实现在电路编程。第四，使用支持该器件的商用EPROM 编程器进行并行编程或擦除。该器件不提供对代码内容的直接校验。而是提供一个扇区或整个用户代码区的32 位CRC 结果附外文原文： P89LPC9521. General descriptionThe P89LPC952 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks,six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC952 in order to reduce component count, board space, andsystem cost.2. Features2.1 Principal features- 8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages.Single-byte erasing allows any byte(s) to be used as non-volatile data storage.-256-byte RAM data memory and a 256-byte auxiliary on-chip RAM.- 8-input multiplexed 10-bit ADC with window comparator that can generate an interrupt for in or out of range results. Two analog comparators with selectable inputs and reference source.-Two 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to become a PWM output) and a 23-bit system timer that can also be used as a RTC.- Two enhanced UARTs with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I2C-bus communication port and SPI communication port.- High-accuracy internal RC oscillator option, with clock doubler option, allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. Fast switching between the internal RC oscillator and any oscillator source provides optimal support of minimal power active mode with fast switching to maximum performance.- 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V).-44-pin packages with 40 I/O pins minimum while using on-chip oscillator and reset options.- Port 5 has high current sourcing/sinking (20 mA) for all Port 5 pins. All other port pins have high sinking capability (20 mA). A maximum limit is specified for the entire chip.- Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values.2.2 Additional features- A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.-Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs.- Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application.- In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application.- Low voltage (brownout) detect allows a graceful system shutdown when power fails. May optionally be configured as an interrupt.- Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 mA (total power-down with voltage comparators disabled).- Active-LOW reset input can be driven by any internal reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.-Only power and ground connections are required to operate the P89LPC952 when internal reset option is selected.- Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz.- Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function.- Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only.- Port input pattern match detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.-Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.- Four interrupt priority levels.- Eight keypad interrupt inputs, plus two additional external interrupt inputs.- Schmitt trigger port inputs.-Second data pointer.-Extended temperature range.附外文原文：The P89LPC952 flash memory General description-The P89LPC952 flash memory provides in-circuit electrical erasure and programming.-The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP and byte-erase allows code memory to be used for non-volatile data storage.On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC952 flash reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC952 uses VDD as the supply voltage to perform the Program/Erase algorithms.Features Programming and erase over the full operating voltage range. Byte erase allows code memory to be used for data storage. Read/Programming/Erase using ISP/IAP/ICP. Internal fixed boot ROM, containing low-level IAP routines available to user code. Default loader providing ISP via the serial port, located in upper end of user program memory. Boot vector allows user-provided flash loader code to reside anywhere in the flash memory space, providing flexibility to the user. Any flash program/erase operation in 2 ms. Programming with industry-standard commercial programmers. Programmable security for the code in the flash for each sector. 100,000 typical erase/program cycles for each byte. 10 year minimum data retention.Flash organization-The program memory consists of eight 1 kB sectors on the P89LPC952 devices. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase,and byte erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.Using flash as data storage-The flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the secto