并行乘法器.doc

EDA技术与应用实验报告 实验名称：并行乘法器姓 名：陈丹学 号：100401202班 级：电信（2）班时 间：2012.12.18南京理工大学紫金学院电光系一、实验目的1）学习包集和元件例化语句的使用。2）学习FAU（全加器单元）电路的设计。3）学习并行乘法器电路的设计二、实验原理1）用VHDL代码描述FAU、与门电路，要求其操作数有a,b两个，每个操作数都是4位宽度。2）利用元件例化语句构成所需要的基本元件，利用包集声明该元件，在主代码中调用该元件完成设计。三、实验内容6,1并行乘法器的VHDL描述 首先给出两个元件：2端口与门，全加器，然后由这两种元件构成并行乘法器6.21 全加器的设计 全加器的表达式为新建VHDL文件 出入代码将文件保存为adder.vhdlibrary ieee;use ieee.std_logic_1164.all;entity adder isport(a,b,cin:in std_logic;s,c:out std_logic);end adder;architecture rhg of adder isbegins=a xor b xor cin;c=(a and b) or (a and cin) or (b and cin);end rhg;6.2.2 与门新建VHDL文件 出入代码将文件保存为and_2.vhdlibrary ieee;use ieee.std_logic_1164.all;entity and_2 isport(a,b:in std_logic;y:out std_logic);end;architecture rhg of and_2 isbeginy=a and b;end rhg;编译 保存 6.2.3 package 定义新建VHDL文件 输入package定义的VHDL代码 存为my_components.vhdlibrary ieee;use ieee.std_logic_1164.all;package my_components iscomponent and_2 isport(a,b:in std_logic;y:out std_logic);end component;component adder isport(a,b,cin:in std_logic;s,c:out std_logic);end component;end my_components;6.2.4 设计top 单元library ieee;use ieee.std_logic_1164.all;use work.my_components.all;entity top isport(a:in std_logic;b:in std_logic_vector(3 downto 0);s,c:out std_logic_vector(2 downto 0);p:out std_logic);end;architecture rhg of top isbeginb1: and_2 port map(a,b(3),s(2);b2: and_2 port map(a,b(2),s(1);b3: and_2 port map(a,b(1),s(0);b4: and_2 port map(a,b(0),p);c=000;end rhg;6.2.4 设计mid 单元library ieee;use ieee.std_logic_1164.all;use work.my_components.all;entity mid isport(a:in std_logic; b:in std_logic_vector(3 downto 0); sin,cin:in std_logic_vector(2 downto 0); sout,cout:out std_logic_vector(2 downto 0); p:out std_logic);end;architecture rhg of mid issignal and_out:std_logic_vector(2 downto 0);beginb1: and_2 port map(a,b(3),sout(2);b2: and_2 port map(a,b(2),and_out(2);b3: and_2 port map(a,b(1),and_out(1);b4: and_2 port map(a,b(0),and_out(0);b5: adder port map(sin(2),cin(2),and_out(2),sout(1),cout(2);b6: adder port map(sin(1),cin(1),and_out(1),sout(0),cout(1);b7: adder port map(sin(0),cin(0),and_out(0),p,cout(0);end rhg;6.2.5 lower 单元设计library ieee;use ieee.std_logic_1164.all;use work.my_components.all;entity lower isport(sin,cin:in std_logic_vector(2 downto 0); p:out std_logic_vector(3 downto 0);end;architecture rhg of lower issignal local:std_logic_vector(2 downto 0);beginlocal(0)=0;b1:adder port map(sin(0),cin(0),local(0),p(0),local(1);b2:adder port map(sin(1),cin(1),local(1),p(1),local(2);b3:adder port map(sin(2),cin(2),local(2),p(2),p(3);end rhg;6.2.6 package 定义library ieee;use ieee.std_logic_1164.all;package my_com1 iscomponent lower isport(sin,cin:in std_logic_vector(2 downto 0); p:out std_logic_vector(3 downto 0);end component;component mid isport(a:in std_logic; b:in std_logic_vector(3 downto 0); sin,cin:in std_logic_vector(2 downto 0); sout,cout:out std_logic_vector(2 downto 0); p:out std_logic);end component;component top isport(a:in std_logic; b:in std_logic_vector(3 downto 0); s,c:out std_logic_vector(2 downto 0); p:out std_logic);end component;end my_com1;6.2.7 设计并行乘法器library ieee;use ieee.std_logic_1164.all;use work.my_components.all;use work.my_com1.all;entity multiplier is port(a,b:in std_logic_vector(3 downto 0); p:out std_logic_vector(7 downto 0);end;architecture rhg of multiplier is type matrix is array (0 to 3) of std_logic_vector(2 downto 0);signal s,c:matrix;beginb1:top port map(a(0),b,s(0),c(0),p(0);b2:mid port map(a(1),b,s(0),c(0),s(1),c(1),p(1);b3:mid port map(a(2),b,s(1),c(1),s(2),c(2),p(2);b4:mid port map(a(3),b,s(2),c(2),s(3),c(3),p(3);b5:lower por