verilogHDL分频器(奇数分频和偶数分频).docx

module clk_div(/-input-iCLK,div,/-output-oCLK);/-input-parameterWIDE=14;inputiCLK;inputWIDE-1:0div;/-output-outputoCLK;wire oCLK_odd;wireoCLK_even;assign oCLK=div0?oCLK_odd:oCLK_even;div_odd DUTo (.iCLK(iCLK),.oCLK(oCLK_odd),.div(div);div_even DUTe (.iCLK(iCLK),.oCLK(oCLK_even),.div(div);endmodule/ oddmodule div_odd(/-input-iCLK,div,/-output-oCLK);/-input-parameterWIDE=14;input iCLK;inputWIDE-1:0div;/-output-outputoCLK;regoutCLK;/*=solve 1=regcout;regWIDE-1:0cnt;initialcnt=0;wireinCLK;regcc;initialcc=0;always (posedge cout)cc=cc;assign inCLK = iCLKcc;always (posedge inCLK)beginif(cnt(divWIDE-1:1)begincnt=cnt+1;cout=1b0;endelsebegincnt=0;cout=1b1;endendalways (negedge iCLK)outCLK = cout;assign oCLK=cc;*/=/solve 2/=regWIDE-1:0cnt_a;initialcnt_a=0;regWIDE-1:0cnt_b;initialcnt_b=0;regcout_a;regcout_b;always (negedge iCLK)beginelse if(cnt_a(divWIDE-1:1)&cnt_a(divWIDE-1:0-1)begincout_a=1b0;cnt_a=cnt_a+1;endelsebegincnt_a=0;endendalways (posedge iCLK)beginif(cnt_b(divWIDE-1:1)&cnt_b(divWIDE-1:0-1)begincout_b=1b0;cnt_b=cnt_b+1;endelsebegincnt_b=0;endendassign oCLK = cout_a&cout_b;endmodule/evenmodule div_even(/-input-iCLK,div,/-output-oCLK);/-input-parameterWIDE=14;input iCLK;inputWIDE-1:0div;/-output-outputoCLK;regoCLK;initialoCLK = 1b0;regWIDE-1:0cnt;initialoCLK = 0;always (posedge iCLK)beginif(cnt(divWIDE-1:1-1)cnt = cnt + 1;elsebegincnt = 0;oCLK = oCLK;endendendmodule/=/testbench/=/*module clk_div_test;/-input-parameterWIDE=14;regiCLK;regWIDE-1:0div;/-output-wireoCLK;clk_div cc(.iCLK(iCLK),.div(div),.oCLK(oCLK);always #20 iCLK = iCLK;initialbeginiCLK = 0;div=14d7;#1000 $stop;endendmodule*/module clk_div14bits(clk,a,clkout);input clk,a;output clkout;reg clkout;wire oCLK1,oCLK2;clk_div cc1(.div(14d8),.iCLK(iCLK),.oCLK(oCLK1);clk_div cc2(.div(14d9),.iCLK(iCLK),.oCLK(oCLK2);always (a or posedge clkin)beginif(a=1)clkout=oCLK1;elseclkout=oCLK2;endendmodule/测试代码/testbenchmodule clk_div14bits_test;/-input-parameterWIDE=14;regclk;regWIDE-1:0div;/-output-wireoCLK;clk_div14bits cc3(.clk(clk),.a(a