24小时数字时钟的VHDL程序 2012.doc

24小时数字时钟的VHDL程序 2012-4-20 23:24阅读(37)先编辑一个74LS161十进制计数器：Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity court161 is port( clk,CTT,CTP,LD,CR:in std_logic; D3,D2,D1,D0: in std_logic; Q:out std_logic_VECTOR(3 DOWNTO 0); Co: out std_logic);end court161; architecture court of court161 is signal a,b,c: std_logic ;signal D,CQI:std_logic_vector(3 downto 0); begin D=D3&D2&D1&D0; a=CTT and CTP; b=(not (CQI(3) and CQI(0)and LD; process(clk,CTT,CTP,LD,CR,D3,D2,D1,D0) begin if a=1 then if clkevent and clk=1 then if b=0 then CQI=D; else CQI=CQI+1; end if; end if; if CQI=9 then c=1; else c=0; end if; end if; if clkevent and clk=1 then Co=c; end if; if CR=0 then CQI=0000; end if; Qyyyyyyyyyynull; end case; a=y(6);b=y(5);c=y(4); d=y(3);e=y(2);f=y(1);g=y(0); end process; end;然后在编写时钟描述语言Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity timer24 is port(CP,CR:IN STD_LOGIC; AS0,BS0,CS0,DS0,ES0,FS0,GS0,AS1,BS1,CS1,DS1,ES1,FS1,GS1:OUT STD_LOGIC; AM0,BM0,CM0,DM0,EM0,FM0,GM0,AM1,BM1,CM1,DM1,EM1,FM1,GM1:OUT STD_LOGIC; AH0,BH0,CH0,DH0,EH0,FH0,GH0,AH1,BH1,CH1,DH1,EH1,FH1,GH1:OUT STD_LOGIC);END TIMER24;architecture TIMER of TIMER24 is signal H1,H0,M1,M0,S1,S0:std_logic_vector(3 downto 0);SIGNAL C0,C1,C2,C3,C4,C5: std_logic ;COMPONENT court161 IS port( clk,CTT,CTP,LD,CR:in std_logic; D3,D2,D1,D0: in std_logic; Q:out std_logic_VECTOR(3 DOWNTO 0); Co: out std_logic);end COMPONENT; COMPONENT QDLED7 IS PORT(DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0); a,b,c,d,e,f,g:out std_logic); end COMPONENT; begin U0:court161 PORT MAP(CP,1,1,1,CR,0,0,0,0,S0,C0); U1:court161 PORT MAP(C0,1,1,(NOT(S1(2)AND S1(0),CR,0,0,0,0,S1,C1); U2:court161 PORT MAP(NOT(S1(2)AND S1(0),1,1,1,CR,0,0,0,0,M0,C2); U3:court161 PORT MAP(C2,1,1,(NOT(M1(2)AND M1(0),CR,0,0,0,0,M1,C3); U4:court161 PORT MAP(C3,1,1,1,(CR AND(NOT(H1(1) AND H0(2),0,0,0,0,H0,C4); U5:court161 PORT MAP(C4,1,1,(NOT H1(1),(CR AND(NOT(H1(1) AND H0(2),0,0,0,0,H1,C5); U6:QDLED7 PORT MAP(S0,AS0,BS0,CS0,DS0,ES0,FS0,GS0); U7:QDLED7 PORT MAP(S1,AS1,BS1,CS1,DS1,ES1,FS1,GS1); U8:QDLED7 PORT MAP(M0,AM0,BM0,CM0,DM0,EM0,FM0,GM0); U9:QDLED7 PORT MAP(M1,AM1,BM1,CM1,DM1,EM1,FM1,GM1); U10:QDLED7 PORT MAP(H0,AH0,BH0,CH0,DH0,EH0,FH0,GH0); U11:QDLED7 PORT MAP(H1,AH1,BH1,CH1,DH1,EH1,FH1,GH1); END;接上数码管，和脉冲信号发生器，必要时要分频，分成脉冲周期为1秒的脉冲周期方可。一般电路里的晶振频率都很高，在设计秒表或钟表时，需要将频率很高的脉冲变成频率为1Hz的脉冲，就可作为计时的标准单位，这个过程叫分频，下面是将6MHz的频率分频为周期是1秒的分频电路程序，即用2个计数200和一个计数150的三个计数器串联而成，这样200*200*150=6000000，即三个合起来计数6000000次刚好为1秒：Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;entity fenpin6M is port(cp:in std_logic; clk:out std_logic);end fenpin12M;Architecture fen of fenpin12M is signal Q0,Q1,Q2:std_logic_vector(7 downto 0); signal c0,c1,c2:std_logic; begin process(cp,c0,c1) begin if cpevent and cp=1 then if Q0199 then Q0=Q0+1; else Q0=00000000; end if; if Q0=199 then c0=1; else c0=0; end if; end if; if c0event and c0=1 then if Q1149 then Q1=Q1+1; else Q1=00000000; end if; if Q1=149 then c1=1; else c1=0; end if