用Verilog HDL设计2位16进制计数器.doc

基于FPGA的系统设计与应用 实验二 计数器设计实验 一、实验目的： 学习计数器的设计、仿真和硬件测试方法。二、实验内容及步骤： 1.用Verilog HDL设计2位16进制计数器，由DE2的KEY0输入计数值，在HEX1，HEX0上显示计数值。 2.使用嵌入式逻辑分析仪进行仿真； 3.将实验程序下载到DE2运行。实验注意事项：去抖动三、程序代码module lib22(out1,out2,clk,rst,key);output 6:0 out1,out2;input clk,rst;input key;reg 19:0count;reg 7:0in;reg 6:0out1,out2;reg C,K;reg 9:0 r1;always(posedge clk) if(count=20d5000) begin C=C; count=1b0; end else count=count+1b1;always (posedge C) begin if(r110d1000) begin K=1b0; r1=r1+1b1; end else begin K=1b1; r1=1b0; end endalways (posedge C,negedge rst) if(!rst) in=1b0; else if(!K) begin in=in+8b1; endalways (in3:0) case(in3:0) 4b0000:out1=7b1000000; 4b0001:out1=7b1111001; 4b0010:out1=7b0100100; 4b0011:out1=7b0110000; 4b0100:out1=7b0011001; 4b0101:out1=7b0010010; 4b0110:out1=7b0000010; 4b0111:out1=7b1011000; 4b1000:out1=7b0000000; 4b1001:out1=7b0010000; 4b1010:out1=7b0001000; 4b1011:out1=7b0000011; 4b1100:out1=7b1000110; 4b1101:out1=7b1100001; 4b1110:out1=7b0000110; 4b1111:out1=7b0001110; default:out1=7b1111111; endcasealways (in7:4) case(in7:4) 4b0000:out2=7b1000000; 4b0001:out2=7b1111001; 4b0010:out2=7b0100100; 4b0011:out2=7b0110000; 4b0100:out2=7b0011001; 4b0101:out2=7b0010010; 4b0110:out2=7b0000010; 4b0111:out2=7b1011000; 4b1000:out2=7b0000000; 4b1001:out2=7b0010000; 4b1010:out2=7b0001000; 4b1011:out2=7b0000011; 4b1100:out2=7b1000110; 4b1101:out2=7b1100001; 4b1110:out2=7b0000110; 4b1111:out2=7b0001110; default:out2=7b1111111; endcase endmodule四、实验原理图：DE2按键电路图五、实验总结与分析：1.不加去斗时，出现的结果不稳定，不同的DE2板子结果不一样，在加上去