AD9959数据手册部分内容中文翻译.doc

AD9959数据手册（部分）GENERAL DESCRIPTION概述The AD9959 consists of four direct digital synthesizer (DDS) cores that provide independent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing, such as filtering, amplification, or PCB layout-related mismatches. Because all channels share a common system clock, they are inherently synchronized. Synchronization of multiple devices is supported. The AD9959 can perform up to a 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9959 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation.AD9959含有四个直接数字频率合成器（DDS），提供各通道独立的频率、相位和振幅控制。这种灵活性可以用来纠正信号之间的不平衡，这种不平衡是由于模拟处理，如滤波，放大，或PCB布局相关的不匹配导致。因为所有通道共用一个系统时钟，因此固有的同步。也支持多个设备的同步。AD9959可以执行16级频率、相位、振幅（FSK，PSK，ASK）调制，通过将数据传到配置引脚执行。此外，AD9959还支持频率、线性扫频、相位或振幅的应用，如雷达和仪表。The AD9959 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPI- compatible mode of operation that is virtually identical to the SPI operation found in earlier Analog Devices, Inc., DDS products. Flexibility is provided by four data pins (SDIO_0/SDIO_1/ SDIO_2/SDIO_3) that allow four programmable modes of serial I/O operation.AD9959的串行I/O端口提供了多种配置，提供显著的灵活性。串行I / O端口提供了一个SPI兼容的操作模式， SPI操作与较早的模拟设备公司DDS产品几乎相同。灵活性是通过四个数据引脚（sdio_0 / sdio_1 /sdio_2 / sdio_3）允许四可编程串行I/O操作模式来实现的。The AD9959 uses advanced DDS technology that provides low power dissipation with high performance. The device incorporates four integrated, high speed 10-bit DACs with excellent wideband and narrow-band SFDR. Each channel has a dedicated 32-bit frequency tuning word, 14 bits of phase offset, and a 10-bit output scale multiplier.AD9959采用先进的DDS技术，提供低高性能低功耗。该器件集成了四个高速10位DAC具有优良的宽带和窄带SFDR。每个通道有一个专门的32位频率调谐字，14位相位偏移，和一个10位幅度调节输出。The DAC outputs are supply referenced and must be terminated into AVDD by a resistor or an AVDD center-tapped transformer. Each DAC has its own programmable reference to enable different full-scale currents for each channel. The DDS acts as a high resolution frequency divider with the REFCLK as the input and the DAC providing the output. The REFCLK input source is common to all channels and can be driven directly or used in combination with an integrated REFCLK multiplier (PLL) up to a maximum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REFCLK input also features an oscillator circuit to support an external crystal as the REFCLK source. The crystal must be between 20 MHz and 30 MHz. The crystal can be used in combination with the REFCLK multiplier.DAC的输出供给参考必须通过电阻接到AVDD或接到AVDD中心抽头变压器。每个DAC有自己的可编程参考，能提供各通道的不同满量程电流。REFCLK作为输入时，DDS核心作为一个高分辨率分频器，以DAC提供输出。REFCLK输入源对所有通道是一样的，可直接驱动或用于与一个集成的REFCLK乘法器组合（PLL），最高500 MSPS。PLL倍增因子可编程，从4到20的整数。REFCLK输入还可作为一个振荡器电路，支持外部晶振作为参考源。该晶振必须介于20兆赫和30兆赫。晶振可用于与REFCLK倍频组合。The AD9959 comes in a space-saving 56-lead LFCSP package. The DDS core (AVDD and DVDD pins) is powered by a 1.8 V supply. The digital I/O interface (SPI) operates at 3.3 V and requires DVDD_I/O (Pin 49) be connected to 3.3 V. The AD9959 operates over the industrial temperature range of 40C to +85C.AD9959使用节省空间的56引脚LFCSP封装。DDS的核心（AVDD和DVDD引脚）由1.8 V供电。数字I / O接口（SPI）的工作在3.3 V，要求dvdd_I/O（引脚49）连接到3.3 V。AD9959可运行在超过工业温度范围的-40C到85C。ABSOLUTE MAXIMUM RATINGS 绝对最大额定值Table 2. 表2Parameter参数 Rating 额定值Maximum Junction Temperature 最大结温150C DVDD_I/O (Pin 49) 4 V AVDD, DVDD 2 V Digital Input Voltage (DVDD_I/O = 3.3 V)数字输入电压0.7 V to +4 V Digital Output Current数字输出电流 5 mA Storage Temperature Range 存储温度65C to +150C Operating Temperature Range操作温度 40C to +85C Lead Temperature (10 sec Soldering) 焊接温度300C JA 21C/W JC 2C/WTable 3. Pin Function Descriptions引脚说明引脚助记符I/O14针描述3MASTER_RESETI6高电平有效复位引脚；将使AD9959内部寄存器复位到缺省状态，如寄存器图和位描述部分的描述。4PWR_DWN_CTLI4外部电源控制（PDC）40-43P0-P3I1、35、7用于调制(FSK,PSK,ASK)的数据引脚,启动/停止扫频累加器或用于输出幅度的斜坡上升或下降.数据同步于引脚SYNC_CLK (同步时钟 54脚).数据必需满足SYNC_CLK 设置和保持时间的要求;引脚的功能由数据配置说明位(PPC)控制(FR114:12).46IO_UPDATEI8上升沿使I/O口缓冲中的数据传送到活动寄存器。数据同步于引脚SYNC_CLK (同步时钟 54脚). IO_UPDATE必需满足SYNC_CLK 设置和保持时间的要求，以保证到DAC输出的数据有固定的延迟管道，否则，不确定有1个同路时钟（SYNC_CLK）周期的数据管道存在。最小的脉冲宽度是1个同步时钟周期。47I10低电平片选；允许多器件共用I/O总线。48SCLKI12I/O操作的串行数据时钟；数据位在SCLK的上升沿写入，在下降沿读取。50SDIO_0I/O9串行数据引脚51 51SDIO_1 SDIO_2I/O11、13用于串行数据引脚或启动输出幅度的斜坡上升或下降53SDIO_3I/O14用于串行数据引脚或启动输出幅度的斜坡上升或下降；在单位或2位模式，此引脚用于SYNC_I/O。如果SYNC_I/O功能未使用，连接到地或逻辑0。在单位或者2位模式中，不要让此引脚浮地。THEORY OF OPERATION 操作原理DDS CORE DDS核心The AD9959 has four DDS cores, each consisting of a 32-bit phase accumulator and phase-to-amplitude converter. Together, these digital blocks generate a digital sine wave when the phase accumulator is clocked and the phase increment value (frequency tuning word) is greater than 0. The phase-to-amplitude converter simultaneously translates phase information to amplitude information by a cos() operation. The output frequency (fOUT) of each DDS channel is a function of the rollover rate of each phase accumulator. The exact relationship is given in the following equation:AD9959有四个DDS内核，每个含32相位累加器和相位-幅度转换器。这些数字模块在一起产生数字正弦波，当相位累加器的时钟和相位增量值（频率调谐字）大于0。相位幅度转换器同时通过COS（）操作，转换相位信息到幅度信息。每个DDS通道输出频率（fout）是每个相位累加器的转换函数。确切的关系在下面的等式中给出：fout=FTW(fs)232where: fS is the system clock rate. FTW is the frequency tuning word and is 0 FTW 231. 232 represents the phase accumulator capacity.其中：fs是系统时钟速率。FTW是频率调谐字和0FTW231。232表示相位累加器容量。Because all four channels share a common system clock, they are inherently synchronized. 因为所有四个通道共用一个系统时钟，他们是本质同步的。The DDS core architecture also supports the capability to phase offset the output signal, which is performed by the channel phase offset word (CPOW). The CPOW is a 14-bit register that stores a phase offset value. This value is added to the output of the phase accumulator to offset the current phase of the output signal. Each channel has its own phase offset word register. This feature can be used for placing all channels in a known phase relationship relative to one another. The exact value of phase offset is given by the following equation:=POW214360DDS的核心架构还支持输出信号的相位偏移，由信道的相位偏移（cpow）字实现。cpow是一个14位的寄存器，存储相位偏移值。此值添加到相位累加器的输出，偏移电流信号相位。每个通道都有自己的相位偏移字寄存器。此功能可用于设置所有通道的相位相关关系。相位偏移量实际值由以下方程给出：DIGITAL-TO-ANALOG CONVERTER数模转换The AD9959 incorporates four 10-bit current output DACs. The DAC converts a digital code (amplitude) into a discrete analog quantity. The DAC current outputs can be modeled as a current source with high output impedance (typically 100 k). Unlike many DACs, these current outputs require termination into AVDD via a resistor or a center-tapped transformer for expected current flow.AD9959采用四个10位电流输出DAC。DAC将数字代码（幅度）转换成离散的模拟量。DAC的电流输出可以被建模为高输出阻抗的电流源（通常为100 K）。不像许多DAC，这些电流输出要求通过电阻器或中心抽头变压器接到AVDD以获得预期的电流。Each DAC has complementary outputs that provide a combined full-scale output current (IOUT + I). The outputs always sink current, and their sum equals the full-scale current at any point in time. The full-scale current is controlled by means of an external resistor (RSET) and the scalable DAC current control bits discussed in the Modes of Operation section. The resistor, RSET, is connected between the DAC_RSET pin and analog ground (AGND). The full-scale current is inversely proportional to the resistor value as follows:Rset=18.91Iout(max)每个DAC互补输出提供一个组合的满量程输出电流（输出电流和输入电流）。输出总是吸收电流，在任何时间点它们的和等于满量程电流。满量程电流通过一个外部电阻器（RSET）控制和操作模式部分中讨论的DAC的电流位进行尺度控制。电阻RSET，连接DAC_REST脚和模拟地（AGND）之间。满量程电流与电阻值成反比：The maximum full-scale output current of the combined DAC outputs is 15 mA, but limiting the output to 10 mA provides optimal spurious-free dynamic range (SFDR) performance. The DAC output voltage compliance range is AVDD + 0.5 V to AVDD 0.5 V. Voltages developed beyond this range may cause excessive harmonic distortion. Proper attention should be paid to the load termination to keep the output voltage within its compliance range. Exceeding this range could potentially dam-age the DAC output circuitry.最大满量程的输出组合DAC电流为15 mA，但限制输出到10毫安以提供最优的无杂散动态范围（SFDR）性能。DAC的输出电压范围为AVDD + 0.5 V电压AVDD0.5V。超出了这个范围可能会导致谐波失真过大。应注意负载，以保持其输出电压在其合规范围。超过这个范围可能损坏DAC输出电路。MODES OF OPERATION操作模式There are many combinations of modes (for example, single- tone, modulation, linear sweep) that the AD9959 can perform simultaneously. However, some modes require multiple data pins, which can impose limitations. The following guidelines can help determine if a specific combination of modes can be performed simultaneously by the AD9959.有许多组合模式（例如，单音，调制，线性扫频），AD9959能够同时进行。然而，一些模式需要多个数据引脚，它可以施加限制。下面的指南可以帮助确定模式的特定组合是否可以用AD9959同时进行。CHANNEL CONSTRAINT GUIDELINES通道约束准则Single-tone mode, two-level modulation mode, and linear sweep mode can be enabled on any channel and in any combination at the same time单音模式，两电平调制模式，线性扫频繁模式，可以启用在任何通道，并在同一时间任何组合。Any one or two channels in any combination can perform four-level modulation. The remaining channels can be in single-tone mode.任何一个或两个通道可在任何组合执行四电平调制。剩余的通道可以在单音模式。Any channel can perform eight-level modulation. The three remaining channels can be in single-tone mode.任何一个通道都可以执行八电平调制。三个剩余信道可以在单音模式。Any channel can perform 16-level direct modulation. The three remaining channels can be in single-tone mode.任何一个通道都可以执行16电平直接调制。三个剩余信道可以在单音模式。The RU/RD function can be used on all four channels in single-tone mode. See the Output Amplitude Control Mode section for the RU/RD function.所有四个通道可以在单音模式下使用RU / RD功能。见输出幅度控制块。When Profile Pin P2 and Profile Pin P3 are used for RU/RD, any two channels can perform two-level modulation with RU/RD or any two channels can perform linear frequency or phase sweep with RU/RD. The other two channels can be in single-tone mode. 当配置引脚P2和配置引脚P3用于RU/ RD，任何两个通道可以执行二电平调制与RU/ RD，或任何两个通道可以执行线性频率或相位扫描与RU/RD。其他两个通道可以处于单音模式。When Profile Pin P3 is used for RU/RD, any channel can be used in eight-level modulation with RU/RD. The other three channels can be in single-tone mode. 当配置引脚P3用于RU/ RD，任何通道可以用在八电平调制与RU/RD，另三通道可以在单音模式。 When the SDIO_1, SDIO_2, and SDIO_3 pins are used for RU/RD, any one or two channels, any three channels, or all four channels can perform two-level modulation with RU/RD. Any channels not in the two-level modulation can be in single-tone mode. 当sdio_1，sdio_2，和sdio_3引脚用于RU/RD，任何一个或两个通道，三通道，四通道或可以进行两级调制。其它任何通道不在两级调制的，可以处于单音模式。 When the SDIO_1, SDIO_2, and SDIO_3 pins are used for RU/RD, any one or two channels can perform four-level modulation with RU/RD. Any channels not in four-level modulation can be in single-tone mode. 当sdio_1，sdio_2，和sdio_3引脚用于RU/RD，任何一个或两个通道可以进行四级调制。其它任何通道进行单频模式。 When the SDIO_1, SDIO_2, and SDIO_3 pins are used for RU/RD, any channel can perform 16-level modulation with RU/RD. The other three channels can be in single-tone mode. 当sdio_1，sdio_2，和sdio_3引脚用于RU/RD，任何一个通道可以进行16级调制，其他三个渠道可以在单频模式。 Amplitude modulation, linear amplitude sweep modes, and the RU/RD function cannot operate simultaneously, but frequency and phase modulation can operate simultaneously as the RU/RD function.振幅调制，线性振幅扫描模式，和RU/ RD功能不能同时操作，但是，频率和相位调制可以同时随着RU/RD功能操作。POWER SUPPLIES 电源供应The AVDD and DVDD supply pins provide power to the DDS core and supporting analog circuitry. These pins connect to a 1.8 V nominal power supply. The DVDD_I/O pin connects to a 3.3 V nominal power supply. All digital inputs are 3.3 V logic except for the CLK_MODE_SEL input. CLK_MODE_SEL (Pin 24) is an analog input and should be operated by 1.8 V logic.AVDD和DVDD引脚提供DDS核心的电力供应，和支持模拟电路。这些引脚连接到1.8 V额定电源。dvdd_I/O引脚连接到3.3 V额定电源。所有数字输入3.3 V逻辑，除了clk_mode_sel输入。clk_mode_sel（引脚24）是一个模拟输入和应由1.8伏逻辑操作。SINGLE-TONE MODE 单音模式Single-tone mode is the default mode of operation after a master reset signal. In this mode, all four DDS channels share a common address location for the frequency tuning word (Register 0x04) and phase offset word (Register 0x05). Channel enable bits are provided in combination with these shared addresses. As a result, the frequency tuning word and/or phase offset word can be independently programmed between channels (see the following Step 1 through Step 5). The channel enable bits do not require an I/O update to enable or disable a channel.单音模式是主复位信号后的缺省操作模式。在这种模式下，所有四个DDS通道共享频率调谐字（寄存器0x04）和相位偏移字（寄存器0x05）。通道使能位与这些共享地址组合使用。作为结果，频率调谐字和/或相位偏移字可以在通道之间独立编程（见下面步骤1到步骤5）。通道使能位不要求I/O更新使能或禁用信道。See the Register Maps and Bit Descriptions section for a description of the channel enable bits in the channel select register (CSR, Register 0x00). The channel enable bits are enabled or disabled immediately after the CSR data byte is written.请参见寄存器映射和位描述部分，信道使能位的描述在通道选择寄存器（CSR，寄存器0x00）。在CSR数据字节写入后，通道使能位立即使能或禁用。Address sharing enables channels to be written simultaneously, if desired. The default state enables all channel enable bits. Therefore, the frequency tuning word and/or phase offset word is common to all channels but written only once through the serial I/O port.如果需要的话，地址共享使信道能够同时写入。默认状态启用所有通道使能位。因此，频率调谐字和/或相位偏移字是所有通道共用的，可以只通过串行输入输出端口写一次。The following steps present a basic protocol to program a different frequency tuning word and/or phase offset word for each channel using the channel enable bits.下面的步骤介绍了一个基本的协议，用来使用通道使能位对每个通道编程实现不同频率调谐字和/或相位偏移字。1Power up the DUT and issue a master reset. A master reset places the part in single-tone mode and single-bit mode for serial programming operations (refer to the Serial I/O Modes of Operation section). Frequency tuning words and phase offset words default to 0 at this point.DUT上电和执行主复位。主复位将部件置于单音模式和单位模式串行编程操作（参照串行I/O模式操作部分）。频率调谐字和相位偏移字默认为0在这一点上。2. Enable only one channel enable bit (Register 0x00) and disable the other channel enable bits.只让一个通道使能位使能（寄存器0x00）和禁用其他通道使能位。3. Using the serial I/O port, program the desired frequency tuning word (Register 0x04) and/or the phase offset word (Register 0x05) for the enabled channel.使用串行I/O口，为使能通道的频率调谐字（寄存器0x04）和/或相位偏移字（寄存器0x05）编程。4. Repeat Step 2 and Step 3 for each channel.每个通道重复步骤2和步骤3。5Send an I/O update signal. After an I/O update, all channels should output their programmed frequency and/or phase offset value.发送I/O更新信号。在I/O更新后，所有通道应输出其编程频率和/或相位偏移值。Single-Tone ModeMatched Pipeline Delay单音模式匹配管道延迟In single-tone mode, the AD9959 offers matched pipeline delay to the DAC input for all frequency, phase, and amplitude changes. This avoids having to deal with different pipeline delays between the three input ports for such applications. The feature is enabled by asserting the matched pipe delays active bit found in the channel function register (CFR, Register 0x03). This feature is available in single-tone mode only在单频模式，对于DAC输入的所有频率，相位和振幅的变化提供相匹配的AD9959管道延迟。这避免了此类应用处理这些三个输入端口之间的不同管道延迟。该功能是通过维持在通道功能寄存器（CFR，寄存器0x03）中的匹配管道延迟活动位实现。此功能仅适用于单音模式。REFERENCE CLOCK MODES参考时钟模式The AD9959 supports multiple reference clock configurations to generate the internal system clock. As an alternative to clocking the part directly with a high frequency clock source, the system clock can be generated using the internal, PLL-based reference clock multiplier. An on-chip oscillator circuit is also available for providing a low frequency reference signal by connecting a crystal to the clock input pins. Enabling these features allows the part to operate with a low frequency clock source and still provide a high update rate for the DDS and DAC. However, using the clock multiplier changes the output phase noise characteristics. For best phase noise performance, a clean, stable clock with a high slew is required (see Figure 17 and Figure 18). AD9959支持参考时钟的多个配置，产生内部的系统时钟。作为一种选择，部件时钟直接使用一个高频率的时钟源，系统时钟可以使用内部，基于PLL参考时钟乘法器生成。一个片上振荡器电路也可通过连接晶体的时钟输入引脚，提供一个低频参考信号。启用这些功能，允许部件操作低频时钟操作源，仍然可以提供一个高更新速率的DDS和数模转换器。然而，要使用时钟乘法器改变输出相位噪声特性。对于最佳相位噪声性能，高转换速率时一个干净，稳定的时钟是必需的（见图17图18）。SCALABLE DAC REFERENCE CURRENT CONTROL MODE可缩放DAC参考电流控制模式RSET is common to all four DACs. As a result, the full-scale currents are equal by default. The scalable DAC reference can be used to set the full-scale current of each DAC independent from one another. This is accomplished by using the register bits CFR9:8. Table 5 shows how each DAC can be individually scaled for independent channel control. This scaling provides for binary attenuation. RSET是所有四个DAC共用的。其结果是，满量程电流在缺省情况下相等。可缩放DAC参考用于设置每个DAC独立的满量程电流。这是通过使用寄存器位CFR 9:8完成。表5显示了如何让每个DAC可以单独缩放独立的信道控制。这个缩放提供二进制衰减。Table 5. DAC Full-Scale Current 表5 DAC满量程电流CFR9:8 LSB Current State LSB的当前状态11Full scale 全尺度01 Half scale 半尺度10 Quarter scale 四分之一尺度00 Eighth scale 八分之一尺度POWER-DOWN FUNCTIONS断电功能The AD9959 supports an externally controlled power-down feature and the more common software programmable power-down bits found in previous Analog Devices DDS products. The software control power-down allows the input clock circuitry, the DAC, and the digital logic (for each separate channel) to be individually powered down via unique control bits (CFR7:6). These bits are not active when the externally controlled power-down pin (PWR_DWN_CTL) is high. When the input pin, PWR_DWN_CTL, is high, the AD9959 enters a power-down mode based on the FR16 bit. When the PWR_DWN_CTL input pin is low, the external power-down control is inactive. When FR16 = 0 and the PWR_DWN_CTL input pin is high, the AD9959 is put into a fast recovery power-down mode. In this mode, the digital logic and the DAC digital logic are powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are not powered down.AD9959支持外部控制的断电功能和更常见的软件可编程断电位，同AD公司以前的DDS产品。软件控制关机通过唯一的控制位（CFR 7：6 ）允许输入时钟电路，DAC，和数字逻辑（每