FPGA--数字时钟(verilog)

因为本人也是刚学习FPGA的菜鸟，所以这个程序漏洞很多，仅供参考。/分频子模块MODULEFENPINCLK,RST_N,EN_1S,EN_1MS/产生1S，1MS的分频INPUTCLKINPUTRST_NOUTPUTEN_1SOUTPUTEN_1MSREG310JISHU_1SREG150JISHU_1MSPARAMETERCNT_1S49999999PARAMETERCNT_1MS49999ALWAYSPOSEDGECLKORNEGEDGERST_NBEGINIFRST_NJISHU_1S32B0ELSEIFJISHU_1SCNT_1SJISHU_1SJISHU_1S1B1ELSEJISHU_1S32B0ENDALWAYSPOSEDGECLKORNEGEDGERST_NBEGINIFRST_NJISHU_1MS16B0ELSEIFJISHU_1MSCNT_1MSJISHU_1MSJISHU_1MS1B1ELSEJISHU_1MS16B0ENDASSIGNEN_1SJISHU_1SCNT_1S1B11B0/1SASSIGNEN_1MSJISHU_1MSCNT_1MS1B11B0/1MSENDMODULE/按键控制部分MODULEANJIANCLK,RST_N,KEY1,KEY2,KEY1_LOW,KEY2_LOWINPUTCLKINPUTRST_NINPUTKEY1/分加INPUTKEY2/分减OUTPUTKEY1_LOW/按键按下消抖后的标志位OUTPUTKEY2_LOWREGREG0_KEY/KEY1消抖REGREG1_KEYREGREG2_KEY/KEY2消抖REGREG3_KEYALWAYSPOSEDGECLKORNEGEDGERST_NBEGINIFRST_NBEGINREG0_KEY1B1REG1_KEY1B1ENDELSEBEGINREG0_KEYKEY1REG1_KEYREG0_KEY/根据非阻塞赋值的原理，REG1_KEY存储的值是REG0_KEY上一个时钟的值ENDEND/脉冲边沿检测法,当寄存器KEY1由1变为0时，KEY1_AN的值变为高，维持一个时钟周期WIREKEY1_ANASSIGNKEY1_ANREG1_KEYALWAYSPOSEDGECLKORNEGEDGERST_NBEGINIFRST_NBEGINREG2_KEY1B1REG3_KEY1B1ENDELSEBEGINREG2_KEYKEY2REG3_KEYREG2_KEYENDEND/脉冲边沿检测法,当寄存器KEY2由1变为0时，KEY2_AN的值变为高，维持一个时钟周期WIREKEY2_ANASSIGNKEY2_ANREG3_KEYREG190CNT_KEY1/计数寄存器ALWAYSPOSEDGECLKORNEGEDGERST_NBEGINIFRST_NCNT_KEY120D0/异步复位ELSEIFKEY1_ANCNT_KEY120D0/LED1_AN1，按键确认按下，CNT_KEY1从0开始计数ELSECNT_KEY1CNT_KEY11B1ENDREG190CNT_KEY2/计数寄存器ALWAYSPOSEDGECLKORNEGEDGERST_NBEGINIFRST_NCNT_KEY220D0ELSEIFKEY2_ANCNT_KEY220D0ELSECNT_KEY2CNT_KEY21B1END/以下为消抖程序REGREG_LOWREGREG1_LOWALWAYSPOSEDGECLKORNEGEDGERST_NBEGINIFRST_NBEGINREG_LOW1B1ENDELSEIFCNT_KEY120HFFFFF/时钟50MHZ的话大约计时是20MSBEGINREG_LOWKEY1/LED_AN1，按键确认按下，CNT_KEY从0开始计数，这时候还有消抖动，计数20MS后抖动滤除了此时再锁存一下KEY1的值END/这时KEY1的值就稳定了ENDALWAYSPOSEDGECLKORNEGEDGERST_NBEGINIFRST_NREG1_LOW1B1ELSEREG1_LOWREG_LOWENDASSIGNKEY1_LOWREG1_LOW/当寄存器REG_LOW由1变为0时，KEY_LOW的值变为高，维持一个时钟周期REGREG2_LOWREGREG3_LOWALWAYSPOSEDGECLKORNEGEDGERST_NBEGINIFRST_NBEGINREG2_LOW1B1ENDELSEIFCNT_KEY220HFFFFFBEGINREG2_LOWKEY2ENDENDALWAYSPOSEDGECLKORNEGEDGERST_NBEGINIFRST_NREG3_LOW1B1ELSEREG3_LOWREG2_LOWENDASSIGNKEY2_LOWREG3_LOWENDMODULE/时、分、秒MODULESHIJIANCLK,RST_N,EN_1S,KEY1_LOW,KEY2_LOW,SHI,FEN,MIAOINPUTCLKINPUTRST_NINPUTEN_1SINPUTKEY1_LOWINPUTKEY2_LOWOUTPUT50SHIOUTPUT50FENOUTPUT50MIAOREG50SHIREG50FENREG50MIAOALWAYSPOSEDGECLKORNEGEDGERST_NBEGINIFRST_NBEGINSHI6B0FEN6B0MIAO6B0ENDELSEIFEN_1SBEGINMIAOMIAO1B1IFMIAO60BEGINMIAO0FENFEN1B1IFFEN60BEGINFEN0SHISHI1B1IFSHI24SHI0ENDENDENDELSEIFKEY1_LOWBEGINFENFEN1B1IFFEN60BEGINFEN0SHISHI1B1IFSHI24SHI0ENDENDELSEIFKEY2_LOWBEGINFENFEN1B1IFFEN0BEGINSHISHI1B1FEN59ENDENDELSEBEGINSHISHIFENFENMIAOMIAOENDENDENDMODULE/显示部分MODULEXIANSHICLK,RST_N,EN_1MS,SHI,FEN,MIAO,LED_BIT,DATAOUTINPUTCLKINPUTRST_NINPUTEN_1MSINPUT50SHIINPUT50FENINPUT50MIAOOUTPUT70LED_BIT/位选OUTPUT70DATAOUT/段选/数码管显示09对应段选输出PARAMETERNUM08B11000000,NUM18B11111001,NUM28B10100100,NUM38B10110000,NUM48B10011001,NUM58B10010010,NUM68B10000010,NUM78B11111000,NUM88B10000000,NUM98B10010000REG30SHI1,SHI2,FEN1,FEN2,MIAO1,MIAO2REG70LED_BIT/位选REG70DATAOUT/段选REG20STATE/状态寄存器ALWAYSPOSEDGECLKORNEGEDGERST_NIFRST_NBEGINLED_BIT8B1STATE3B0ENDELSEIFEN_1MSBEGINSTATESTATE1B1SHI1SHI/10SHI2SHI10FEN1FEN/10FEN2FEN10MIAO1MIAO/10MIAO2MIAO10IFSTATE3B000BEGINLED_BIT8B11111110CASEMIAO20DATAOUTNUM01DATAOUTNUM12DATAOUTNUM23DATAOUTNUM34DATAOUTNUM45DATAOUTNUM56DATAOUTNUM67DATAOUTNUM78DATAOUTNUM89DATAOUTNUM9DEFAULTDATAOUTNUM0ENDCASEENDELSEIFSTATE3B001BEGINLED_BIT8B11111101CASEMIAO10DATAOUTNUM01DATAOUTNUM12DATAOUTNUM23DATAOUTNUM34DATAOUTNUM45DATAOUTNUM5DEFAULTDATAOUTNUM0ENDCASEENDELSEIFSTATE3B010BEGINLED_BIT8B11110111CASEFEN20DATAOUTNUM01DATAOUTNUM12DATAOUTNUM23DATAOUTNUM34DATAOUTNUM45DATAOUTNUM56DATAOUTNUM67DATAOUTNUM78DATAOUTNUM89DATAOUTNUM9DEFAULTDATAOUTNUM0ENDCASEENDELSEIFSTATE3B011BEGINLED_BIT8B11101111CASEFEN10DATAOUTNUM01DATAOUTNUM12DATAOUTNUM23DATAOUTNUM34DATAOUTNUM45DATAOUTNUM5ENDCASEENDELSEIFSTATE3B100BEGINLED_BIT8B10111111CASESHI20DATAOUTNUM01DATAOUTNUM12DATAOUTNUM23DATAOUTNUM34DATAOUTNUM4DEFAULTDATAOUTNUM0ENDCASEENDELSEIFSTATE3B101BEGINLED_BIT8B01111111CASESHI10DATAOUTNUM01DATAOUTNUM12DATAOUTNUM2ENDCASEENDELSEIFSTATE3B110BEGINLED_BIT8B11011011DATAOUT8B10111111ENDENDELSEBEGINDATAOUTDATAOUTLED_BITLED_BITENDENDMODULE/顶层模块MODULESHIZHONGCLK,RST_N,KEY1,KEY2,LED_BIT,DATAOUTINPUTCLKINPUTRST_NINPUTKEY1INPUTKEY2OUTPUT70LED_BITOUTPUT70DATAOUTWIREEN_1SWIREEN_1MSWIRE50SHIWIRE50FENWIRE50MIAOWIREKEY1_LOW,KEY2_LOWFENPINFENPIN_INTCLKCLK,RST_NRST_N,EN_1SEN_1S,EN_1MSEN_1MSANJIANANJIAN_INTCLKCLK,RST_NRST_N,KEY1KEY1,KEY2KEY2,KEY1_LOWKEY1_L