VHDL闹钟系统设计

电子与信息工程学院课程设计报告（20102011学年第一学期）本实验用MAXPLUS2软件和GW48实验箱2011年1月课程设计报告1课程设计题目闹钟系统设计及实现目的与任务1、巩固专业基础知识及EDA的相关知识；2、锻炼综合应用所学知识进行小型系统开发设计的能力；3、培养学生将理论应用于实践的能力；4、设计一个简单的闹钟系统。内容和要求要求设计一个带闹钟功能的24小时计时器，计时器的外观如图1所示。TIMEALARMKEY1KEY2图1系统外观它包括以下几个组成部分显示屏4个七段数码管显示当前时间时分或设置的闹钟时间；一个发光二极管以1HZ的频率跳动，用于显示秒；按键KEY1，用于设置调时还是调分；按键KEY2，用于输入新的时间或新的闹钟时间，每按下一次，时或分加1；TIME时间键，用于确定新的时间设置；ALARM闹钟键，用于确定新的闹钟时间设置，或显示已设置的闹钟时间；扬声器，在当前时钟时间与闹钟时间相同时，发出蜂鸣声。课程设计报告2KEY1输入作为计数器的触发信号用来选择数码管LIBRARYIEEEUSEIEEESTD_LOGIC_1164ALLUSEIEEESTD_LOGIC_UNSIGNEDALLENTITYKEY1_TRANS_HJCISPORTCLR_HJCINSTD_LOGICKEY1_HJCINSTD_LOGICQ_HJCBUFFERSTD_LOGIC_VECTOR2DOWNTO0ENDENTITYKEY1_TRANS_HJCARCHITECTUREHJCOFKEY1_TRANS_HJCISBEGINPROCESSCLR_HJC,KEY1_HJCISBEGINIFCLR_HJC1THENQ_HJCN_T_0N_T_1N_T_2N_T_3NULLENDCASEENDIFENDPROCESSNEW_TIME_0_HJC课程设计报告16IFKEY1_HJC1THENNEXT_STATEIFKEY1_HJC1THENNEXT_STATEIFALARM_BUTTON_HJC1THENNEXT_STATEIFTIME_BUTTON_HJC1THENNEXT_STATEIFKEY1_HJC1THENNEXT_STATENULLENDCASEENDPROCESSCOUNT_KEYPROCESSENABLE_COUNT_K,CLK_HJCISBEGIN课程设计报告19IFENABLE_COUNT_K0THENCOUNTER_KKEY_TIMEOUTTHENCOUNT_K_ENDSHOW_ALARM_TIMEOUTTHENCOUNT_A_END1ELSE课程设计报告20COUNTER_ACOUNTER_A1ENDIFENDIFENDPROCESSCOUNT_ALARMENDARCHITECTURE显示驱动模块，是显示新时间还是闹钟时间，还是时钟时间LIBRARYIEEEUSEIEEESTD_LOGIC_1164ALLUSEIEEESTD_LOGIC_UNSIGNEDALLENTITYDISPLAYDRIVER_HJCISPORTALARM_TIME_0_HJCINSTD_LOGIC_VECTOR3DOWNTO0ALARM_TIME_1_HJCINSTD_LOGIC_VECTOR3DOWNTO0ALARM_TIME_2_HJCINSTD_LOGIC_VECTOR3DOWNTO0ALARM_TIME_3_HJCINSTD_LOGIC_VECTOR3DOWNTO0CURRENT_TIME_0_HJCINSTD_LOGIC_VECTOR3DOWNTO0CURRENT_TIME_1_HJCINSTD_LOGIC_VECTOR3DOWNTO0CURRENT_TIME_2_HJCINSTD_LOGIC_VECTOR3DOWNTO0CURRENT_TIME_3_HJCINSTD_LOGIC_VECTOR3DOWNTO0NEW_TIME_0_HJCINSTD_LOGIC_VECTOR3DOWNTO0课程设计报告21NEW_TIME_1_HJCINSTD_LOGIC_VECTOR3DOWNTO0NEW_TIME_2_HJCINSTD_LOGIC_VECTOR3DOWNTO0NEW_TIME_3_HJCINSTD_LOGIC_VECTOR3DOWNTO0SHOW_NEW_TIME_HJCINSTD_LOGICSHOW_A_HJCINSTD_LOGICSOUND_ALARM_HJCOUTSTD_LOGICDISPLAY_0_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0DISPLAY_1_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0DISPLAY_2_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0DISPLAY_3_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0ENDENTITYDISPLAYDRIVER_HJCARCHITECTUREHJCOFDISPLAYDRIVER_HJCISSIGNALDISPLAY_TIME_0STD_LOGIC_VECTOR3DOWNTO0SIGNALDISPLAY_TIME_1STD_LOGIC_VECTOR3DOWNTO0SIGNALDISPLAY_TIME_2STD_LOGIC_VECTOR3DOWNTO0SIGNALDISPLAY_TIME_3STD_LOGIC_VECTOR3DOWNTO0BEGINCTRLPROCESSALARM_TIME_0_HJC,ALARM_TIME_1_HJC,ALARM_TIME_2_HJC,ALARM_TIME_3_HJC,CURRENT_TIME_0_HJC,CURRENT_TIME_1_HJC,CURRENT_TIME_2_HJC,CURRENT_TI课程设计报告22ME_3_HJC,NEW_TIME_0_HJC,NEW_TIME_1_HJC,NEW_TIME_2_HJC,NEW_TIME_3_HJC,SHOW_A_HJC,SHOW_NEW_TIME_HJCISBEGINIFNOTALARM_TIME_0_HJCCURRENT_TIME_0_HJCANDALARM_TIME_1_HJCCURRENT_TIME_1_HJCANDALARM_TIME_2_HJCCURRENT_TIME_2_HJCANDALARM_TIME_3_HJCCURRENT_TIME_3_HJCTHENSOUND_ALARM_HJC0ELSESOUND_ALARM_HJC1ENDIFIFSHOW_NEW_TIME_HJC1THENDISPLAY_TIME_0NEW_TIME_0_HJCDISPLAY_TIME_1NEW_TIME_1_HJCDISPLAY_TIME_2NEW_TIME_2_HJCDISPLAY_TIME_3NEW_TIME_3_HJCELSIFSHOW_A_HJC1THENDISPLAY_TIME_0ALARM_TIME_0_HJCDISPLAY_TIME_1ALARM_TIME_1_HJCDISPLAY_TIME_2ALARM_TIME_2_HJC课程设计报告23DISPLAY_TIME_3ALARM_TIME_3_HJCELSIFSHOW_A_HJC0THENDISPLAY_TIME_0CURRENT_TIME_0_HJCDISPLAY_TIME_1CURRENT_TIME_1_HJCDISPLAY_TIME_2CURRENT_TIME_2_HJCDISPLAY_TIME_3CURRENT_TIME_3_HJCELSEASSERTFALSEREPORT“UNCERTAINDISPLAY_DRIVERCONTROL“SEVERITYWARNINGENDIFENDPROCESSCTRLDISPPROCESSDISPLAY_TIME_0,DISPLAY_TIME_1,DISPLAY_TIME_2,DISPLAY_TIME_3ISBEGINDISPLAY_0_HJCDISPLAY_TIME_0DISPLAY_1_HJCDISPLAY_TIME_1DISPLAY_2_HJCDISPLAY_TIME_2DISPLAY_3_HJCDISPLAY_TIME_3ENDPROCESSDISPENDARCHITECTURE课程设计报告24GW48实验箱扬声器是脉冲驱动，在显示驱动模块产生高电平后与系统时钟相与得脉冲信号LIBRARYIEEEUSEIEEESTD_LOGIC_1164ALLUSEIEEESTD_LOGIC_UNSIGNEDALLENTITYYU_HJCISPORTASOUNDIN_HJCINSTD_LOGICCLK_HJCINSTD_LOGICASOUNDOUT_HJCOUTSTD_LOGICENDENTITYYU_HJCARCHITECTUREHJCOFYU_HJCISBEGINASOUNDOUT_HJCASOUNDIN_HJCANDCLK_HJCENDARCHITECTURE设置新闹钟时间LIBRARYIEEEUSEIEEESTD_LOGIC_1164ALLUSEIEEESTD_LOGIC_UNSIGNEDALLENTITYALARMREG_HJCISPORTNEW_ALARM_TIME_0_HJCINSTD_LOGIC_VECTOR3DOWNTO0NEW_ALARM_TIME_1_HJCINSTD_LOGIC_VECTOR3DOWNTO0NEW_ALARM_TIME_2_HJCINSTD_LOGIC_VECTOR3DOWNTO0课程设计报告25NEW_ALARM_TIME_3_HJCINSTD_LOGIC_VECTOR3DOWNTO0LOAD_NEW_A_HJCINSTD_LOGICCLK_HJCINSTD_LOGICCLR_HJCINSTD_LOGICALARM_TIME_0_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0ALARM_TIME_1_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0ALARM_TIME_2_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0ALARM_TIME_3_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0ENDENTITYALARMREG_HJCARCHITECTUREHJCOFALARMREG_HJCISBEGINPROCESSCLK_HJC,CLR_HJCISBEGINIFCLR_HJC1THENALARM_TIME_0_HJC“0000“ALARM_TIME_1_HJC“0000“ALARM_TIME_2_HJC“0000“ALARM_TIME_3_HJC“0000“ELSEIFRISING_EDGECLK_HJCTHEN课程设计报告26IFLOAD_NEW_A_HJC1THENALARM_TIME_0_HJCNEW_ALARM_TIME_0_HJCALARM_TIME_1_HJCNEW_ALARM_TIME_1_HJCALARM_TIME_2_HJCNEW_ALARM_TIME_2_HJCALARM_TIME_3_HJCNEW_ALARM_TIME_3_HJCELSIFLOAD_NEW_A_HJC/0THENASSERTFALSEREPORT“UNCERTAINLOAD_NEW_ALARMCONTROL“SEVERITYWARNINGENDIFENDIFENDIFENDPROCESSENDARCHITECTUREHJC顶层文件LIBRARYIEEEUSEIEEESTD_LOGIC_1164ALLUSEIEEESTD_LOGIC_UNSIGNEDALLENTITYALARM_HJCISPORTKEY1_HJCINSTD_LOGICKEY2_HJCINSTD_LOGICALARM_BUTTON_HJCINSTD_LOGIC课程设计报告27TIME_BUTTON_HJCINSTD_LOGICCLK_HJCINSTD_LOGICCLK1_HJCOUTSTD_LOGICCLR_HJCINSTD_LOGICDISPLAY_0_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0DISPLAY_1_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0DISPLAY_2_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0DISPLAY_3_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0SOUND_ALARM1_HJCOUTSTD_LOGICENDENTITYALARM_HJCARCHITECTUREHJCOFALARM_HJCISCOMPONENTKEY1_TRANS_HJCISPORTCLR_HJCINSTD_LOGICKEY1_HJCINSTD_LOGICQ_HJCBUFFERSTD_LOGIC_VECTOR2DOWNTO0ENDCOMPONENTCOMPONENTKEY2_TRANS_HJCISPORTCLR_HJCINSTD_LOGICKEY2_HJCINSTD_LOGICQ2_HJCBUFFERSTD_LOGIC_VECTOR3DOWNTO0课程设计报告28ENDCOMPONENTCOMPONENTKEYBUFFER_HJCISPORTKEY1_CTRL_HJCINSTD_LOGIC_VECTOR2DOWNTO0KEY2_HJCINSTD_LOGIC_VECTOR3DOWNTO0CLK_HJCINSTD_LOGICCLR_HJCINSTD_LOGICNEW_TIME_0_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0NEW_TIME_1_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0NEW_TIME_2_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0NEW_TIME_3_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0ENDCOMPONENTCOMPONENTCONTROLLER_HJCISPORTKEY1_HJCINSTD_LOGICALARM_BUTTON_HJCINSTD_LOGICTIME_BUTTON_HJCINSTD_LOGICCLK_HJCINSTD_LOGICCLR_HJCINSTD_LOGICLOAD_NEW_A_HJCOUTSTD_LOGICLOAD_NEW_C_HJCOUTSTD_LOGIC课程设计报告29SHOW_NEW_TIME_HJCOUTSTD_LOGICSHOW_A_HJCOUTSTD_LOGICENDCOMPONENTCOMPONENTALARMREG_HJCISPORTNEW_ALARM_TIME_0_HJCINSTD_LOGIC_VECTOR3DOWNTO0NEW_ALARM_TIME_1_HJCINSTD_LOGIC_VECTOR3DOWNTO0NEW_ALARM_TIME_2_HJCINSTD_LOGIC_VECTOR3DOWNTO0NEW_ALARM_TIME_3_HJCINSTD_LOGIC_VECTOR3DOWNTO0LOAD_NEW_A_HJCINSTD_LOGICCLK_HJCINSTD_LOGICCLR_HJCINSTD_LOGICALARM_TIME_0_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0ALARM_TIME_1_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0ALARM_TIME_2_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0ALARM_TIME_3_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0ENDCOMPONENTCOMPONENTCOUNTER_HJCISPORTNEW_CURRENT_TIME_0_HJCINSTD_LOGIC_VECTOR3DOWNTO0NEW_CURRENT_TIME_1_HJCINSTD_LOGIC_VECTOR3DOWNTO0课程设计报告30NEW_CURRENT_TIME_2_HJCINSTD_LOGIC_VECTOR3DOWNTO0NEW_CURRENT_TIME_3_HJCINSTD_LOGIC_VECTOR3DOWNTO0LOAD_NEW_C_HJCINSTD_LOGICCLK_HJCINSTD_LOGICCLR_HJCINSTD_LOGICCURRENT_TIME_0_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0CURRENT_TIME_1_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0CURRENT_TIME_2_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0CURRENT_TIME_3_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0ENDCOMPONENTCOMPONENTDISPLAYDRIVER_HJCISPORTALARM_TIME_0_HJCINSTD_LOGIC_VECTOR3DOWNTO0ALARM_TIME_1_HJCINSTD_LOGIC_VECTOR3DOWNTO0ALARM_TIME_2_HJCINSTD_LOGIC_VECTOR3DOWNTO0ALARM_TIME_3_HJCINSTD_LOGIC_VECTOR3DOWNTO0CURRENT_TIME_0_HJCINSTD_LOGIC_VECTOR3DOWNTO0CURRENT_TIME_1_HJCINSTD_LOGIC_VECTOR3DOWNTO0CURRENT_TIME_2_HJCINSTD_LOGIC_VECTOR3DOWNTO0CURRENT_TIME_3_HJCINSTD_LOGIC_VECTOR3DOWNTO0NEW_TIME_0_HJCINSTD_LOGIC_VECTOR3DOWNTO0NEW_TIME_1_HJCINSTD_LOGIC_VECTOR3DOWNTO0课程设计报告31NEW_TIME_2_HJCINSTD_LOGIC_VECTOR3DOWNTO0NEW_TIME_3_HJCINSTD_LOGIC_VECTOR3DOWNTO0SHOW_NEW_TIME_HJCINSTD_LOGICSHOW_A_HJCINSTD_LOGICSOUND_ALARM_HJCOUTSTD_LOGICDISPLAY_0_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0DISPLAY_1_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0DISPLAY_2_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0DISPLAY_3_HJCOUTSTD_LOGIC_VECTOR3DOWNTO0ENDCOMPONENTCOMPONENTFQ_HJCISPORTCLK_IN_HJCINSTD_LOGICCLR_HJCINSTD_LOGICCLK_OUT_HJCOUTSTD_LOGICENDCOMPONENTCOMPONENTYU_HJCISPORTASOUNDIN_HJCINSTD_LOGICCLK_HJCINSTD_LOGICASOUNDOUT_HJCOUTSTD_LOGICENDCOMPONENTCOMPONENTFQ1_HJCIS课程设计报告32PORTCLK_IN_HJCINSTD_LOGICCLR_HJCINSTD_LOGICCLK_OUT1_HJCOUTSTD_LOGICENDCOMPONENTSIGNALS0STD_LOGIC_VECTOR2DOWNTO0SIGNALS1,S60,S61,S62,S63,S70,S71,S72,S73,S80,S81,S82,S83STD_LOGIC_VECTOR3DOWNTO0SIGNALS2,S3,S4,S5,S9,S10STD_LOGICBEGINU1KEY1_TRANS_HJCPORTMAPCLR_HJC,KEY1_HJC,S0U2KEY2_TRANS_HJCPORTMAPCLR_HJC,KEY2_HJC,S1U3KEYBUFFER_HJCPORTMAPS0,S1,C