VHDL数字钟设计报告

VHDL数字钟设计报告一数字钟总体设计方案11设计目的正确显示时、分、秒；可手动校时，能分别进行时、分的校正；整点报时功能；12设计思路数字钟的设计模块包括分频器、去抖动电路、校时电路、“时、分、秒”计数器、校时闪烁电路、整点报时和译码显示电路。每一个功能模块作为一个实体单独进行设计，最后再用VHDL的例化语句将各个模块进行整合，生成顶层实体TOP。该数字钟可以实现3个功能计时功能、设置时间功能和报时功能。二数字钟模块细节21分频器（FENPIN）本系统共需3种频率时钟信号（1024HZ、512HZ、1HZ）。为减少输入引脚，本系统采用分频模块，只需由外部提供1024HZ基准时钟信号，其余三种频率时钟信号由分频模块得到。分频原理为以1024HZ基准时钟经1024分频得到512HZ,1HZ频率时钟信号。分频器管脚代码LIBRARYIEEEUSEIEEESTD_LOGIC_1164ALLUSEIEEESTD_LOGIC_UNSIGNEDALLUSEIEEESTD_LOGIC_ARITHALLENTITYFENPINISPORTCLK1024INSTD_LOGICCLK1,CLK512OUTSTD_LOGICENDFENPINARCHITECTURECMLOFFENPINISBEGINPROCESSCLK1024VARIABLECOUNT1INTEGERRANGE0TO512VARIABLEQ1STD_LOGICBEGINIFCLK1024EVENTANDCLK10241THENIFCOUNT1512THENQ1NOTQ1COUNT10ELSECOUNT1COUNT11ENDIFENDIFCLK1DATADATADATADATADATADATADATASEG7SEG7SEG7SEG7SEG7SEG7SEG7SEG7SEG7SEG7SEG7CLK1024,CLK512SCANCLKSIG,CLK1SECCLKSIGU2JIAOSHIPORTMAPRSTRESET,RVSKEY,SELECT_RVSKEYIN0,MTIMEKEYIN1,HCLKINHCLKSIG0,MCLKINMCLKSIG0,HCLKOUTHCLKSIG1,MCLKOUTMCLKSIG1U3HOURPORTMAPRSTRESET,HCLKHCLKSIG1,HOUR1HOUR1SIG0,HOUR0HOUR0SIG0U4MINUTEPORTMAPRSTRESET,MCLKMCLKSIG1,MCOHCLKSIG0,MIN1MIN1SIG0,MIN0MIN0SIG0U5SECONDPORTMAPRSTRESET,SCLKSECCLKSIG,SCOMCLKSIG0,SEC1SEC1SIG,SEC0SEC0SIGU6FLASHJIAOSHIPORTMAPRSTRESET,SCLKSECCLKSIG,RVSKEY,SELECT_RVSKEYIN0,HOUR1INHOUR1SIG0,HOUR0INHOUR0SIG0,MIN1INMIN1SIG0,MIN0INMIN0SIG0,HOUR1OUTHOUR1SIG1,HOUR0OUTHOUR0SIG1,MIN1OUTMIN1SIG1,MIN0OUTMIN0SIG1U7XIANSHIPORTMAPCLK512SCANCLKSIG,H1HOUR1SIG1,H0HOUR0SIG1,M1MIN1SIG1,M0MIN0SIG1,S1SEC1SIG,S0SEC0SIG,SEG7SEG7OUT,SELECT_SIGSELECT_SIGOUTU8BAOSHIPORTMAPCLK1024CLK1024,CLK5