QuartusII时序约束方法

QuartusIISoftwareDesignSeries:TimingAnalysis,2,常见术语的中文翻译,Tsetup:建立时间Thold：保持时间Skew：传输时差,时钟歪斜Slack：余量Fmax：最大频率Inputmaximumdelay：输入最大延时Inputminimumdelay：输入最小延时Outputmaximumdelay：输出最大延时Outputminimumdelay：输出最小延时Maxdelay：最大延时MinDelay：最小延时Recoverytime：恢复时间Removaltime：移去时间Jitter：抖动,3,TimeQuestAgenda,IntroductiontoTimeQuestTimeQuestterminologyreviewUsingTimeQuestExampleApplication,4,TimeQuestTimingAnalyzer,NewtimingengineinQuartusIIProvidetiminganalysissolutionmeetingrequirementsofallusersFPGAdesignbackgroundASICdesignbackgroundEasy-to-useinterfaceStandardreportingThTremExternaldevicedefaultsto1,87,ReportTiming(GUI),ChooseReportTiming(Reportsmenu)ordouble-clickonReportTiming(Taskspane),Selectwheretosendoutputreport,Tcl:report_timing,Selectlevelofdetail,88,SummarySlack/PathReport,report_timing-from_clockc100-to_clockc200-setup-npaths10-detailsummary-panel_name“Setup(c100toc200)Summary,CalculatedSlack,Sourceusewildcardsintargetsorcommand),TimeQuestmain:ConstraintsCreateClockSDCEditor:EditInsertConstraintCreateClock,104,NameFinder,ClickingonBrowsebuttonopensNameFinderallowingyoutosearchnetlistfornodenames(similartoQuartusIINodeFinder),Selectcollectiontosearch,Editcommandhereorfinalcommandtousewildcards,Optionsavailabledependonselectedcollection,105,NameFinderSearchOptions,AlloptionsoffHierarchylevelsinFiltermatchresultsexceptfor*findsallnamesinalllevelsofhierarchyinselectedcollection*|data*findsnamesstartingwithdataatsecondlevelonlyCase-insensitive(allcollections)NamesmatchFilterignoringcapitalizationHierarchical(get_pins;get_cellsonly)Filtermustbejustcellnameorinformof|foo|*findsallpinsoncellnamedfoo*|data*findsallpinsstartingwithdataatanylevelofhierarchyCompatibilitymode(get_pins;get_cellsonly)Alwayssearchesentirehierarchy*|data*findsallpinsstartingwithdataatanylevelofhierarchy*|*|data*performsthesamesearch;extra*|notrequired,106,CreatingaGeneratedClock,Command:create_generated_clockOptions-name-source-master_clock-divide_by-multiply_by-duty_cycle-invert-phase-edges-edge_shift-add,107,create_generated_clockNotes,source:SpeciesthenodeindesignfromwhichgeneratedclockisderivedEx.Placingsourcebeforevs.afteraninverterwouldyielddifferentresultsmaster_clock:Usedifmultipleclocksexistatsourcedueto-addoptionedges:Relatesrising/fallingedgesofgeneratedclocktorising/fallingedgesofsourcebasedonnumberededges-edge_shift:Relatesedgesbasedonamountoftimeshifted(requires-edges),108,CreateGeneratedClockusingGUI,109,GeneratedClockExample1,create_clockperiod10get_portsclk_increate_generated_clocknameclk_divsourceget_pinsinst|clk-divide_by2get_pinsinst|regout,Sourcepin,Targetpin,110,InvertedClockExample,NeedtodefineCLK100addoptionsmanually,123,ClockUncertainty(GUI),124,AutomaticallyDeriveUncertainty,Command:derive_clock_uncertaintyAutomaticallyderiveclockuncertaintiesinsupporteddevicesCycloneIII,StratixII,HardCopyII,StratixIIIUncertaintiescreatedmanuallywithset_clock_uncertaintyhavehigherprecedenceOptions-overwrite:overwritesanyexistinguncertaintyconstraints-add:addsderiveduncertaintiestoexistingconstraintsSDCextensionexpandedwithwrite_sdc-expandNotinGUI,125,TypesofDerivedUncertainties,Inter-clocktransfersTransferswithinasingleclockdomainwithinFPGAIntra-clocktransfersTransfersbetweendifferentclockdomainswithinFPGAI/OinterfaceclocktransfersTransfersbetweenanI/OportandinternaldesignregistersRequirescreationofvirtualclockasreferenceclockforset_input_delayandset_output_delayconstraints(describedlater),126,UndefinedClocks,IssueoccurswhennodesbeingusedasclocksbutnotdefinedwithSDCclockconstraintSolutionUseUnconstrainedPathsReporttofindunconstrainedclocksQuartusIICompilationReporttimingsummaryRunreport_ucpcommandChooseReportUnconstrainedPaths(TasksPaneorReportsmenu),127,UnconstrainedPathReport,UnconstrainedPathsSummaryReportindicateshowmanyclocknodesareunconstrained(alongwithotherunconstrainedpaths),ClockStatusSummaryReportlistseachclockfoundandwhetheritwasconstrained,128,SDCTimingConstraints,ClocksI/OAsynchronouspathsLatchesFalsepathsMulticyclepathsAbsolutedelaysTimeGroups,129,I/OConstraints,CombinatorialI/OinterfaceSynchronousI/OinterfaceSourcesynchronousinterface,130,CombinatorialInterface,Options-from-to-fall_from-rise_from-fall_to-rise_to-through,AllpathsfromINtoOUTneedtobeconstrainedUseset_max_delayFlagsindicatestatusofFIFO,190,FalsePathsonFIFO,FlagGeneration,Cutthesepaths;Useeitherset_false_pathorset_clock_groupsdependingonadditionallogicindesign,191,VerifyingFalsePathssinglecycleholdtransfer,MulticycleSetup=2MulticycleHold=0(Default),S1,S2,H0,H0,*Defaultholdedgeisoneedgebefore/aftersetupedge;holdedgemoveswithsetupedge,Inthisexample,thereisnoenabletopreventpartialdatafrombeingclockedintoREG2,soholdtiminganalysiswillcheckifdatacanarrivetoosoonattheinputtoREG2.,202,UnderstandingMulticycle(2)(cont.),reg1.clk,reg2.clk,Launchedge,Latchedge,Changetoatwocyclesetup;singlecycleholdtransfer,S2,H0,set_multicycle_pathfromget_pinsreg1|regouttoget_pinsreg2|datain-end-setup2,*Defaultholdedgeisoneedgebefore/aftersetupedge;holdedgemoveswithsetupedge,Inthisexample,thereisnoenabletopreventpartialdatafrombeingclockedintoREG2,soholdtiminganalysiswillcheckifdatacanarrivetoosoonattheinputtoREG2.,203,OtherMulticycleCases,PositiveclockphaseshiftoroffsetSourceclockathigherfrequencyUsestartoption,IncorrectLatchedge,CorrectLatchedge,1,2,Noteusingthestartoptionmovesthelatchedgeforwardoneedge(torelaxconstraint),204,ReportingMulticycles,NoMulticycle,205,ReportingMulticycles,SamepathwithSetupMulticycle=2,Latchedgeextendedbyonedestinationclockcycle,206,FPGA,MulticycleExample,#Needtospecifythatthemultiplierisallowed2cyclestocomputearesult#Notethishasalreadybeendeterminedbydesign(half-rateclockenable)set_multicycle_pathfromget_pinsareg*|regoutbreg*|regouttoget_pinsoutreg*|datain-end-setup2,clk,b_in15.0,a_in15.0,result15.0,Twocyclemultiplierbuiltoutoflogic,207,SDCTimingConstraints,ClocksI/OAsynchronouspathsLatchesFalsepathsMulticyclepathsAbsolutedelaysTimeGroups,208,AbsoluteDelays,AppliesatimingvaluetoaparticularpathOverridesthecurrentsetup/holdinformationforthepathderivedfromclockandI/OconstraintsApplyset_max_delay&set_min_delayconstraintstopaths,209,AbsoluteDelayExample,Specifyaninputport-to-registerorregister-to-outputportconstraintwithoutusinginput&outputdelaysUse-rise_from/-fall_from&-rise_to/-fall_totorestricttimingvaluetoonlyregistersrespondingtoarisingorfallingedgetransitionEx.DDRinput,#Applya2nsmaxdelayforaninputportonlytonodesclockedby#therisingedgeofclockCLKset_max_delay-fromget_portsin*-rise_toget_clocksCLK2.000,210,SDCTimingConstraints,ClocksI/OAsynchronouspathsLatchesFalsepathsMulticyclepathsAbsolutedelaysTimeGroups,211,TimeGroups,Defineacustomgroupofnodestowhichyoucanassigntimingassignmentsand/orrequirementsMemberscanincluderegularnodenames,wildcards,and/orothertimegroupnamesCanimproveoverallsoftwareperformanceTcl“set”commandalsosupported,212,TimeGroups,UseQuartusIIsoftwaretocreategroups,Tcl:timegroup-add_member,Members,ExcludedMembers,Create&NameGroup,213,AccessinginTimeQuest,Useget_assignment_groupscollectiontoapplyconstraintstonodesget_assignment_groupsOptions-keepers-ports-registersExampleset_multicycle_pathfromget_assignment_groupssrc_grouptoget_assignment_groupsdst_group2,214,ApplicationExample,DDRInput,215,DDRInputExample,Whatconstraintsdoyouneed?ClockInputdelaymaximum&minimumUsesource-synchronousmethodology,FPGA,datain,clk,Tclk=6ns,DVW,DVW,DVW,DVW,DVW,DVW,Tsu=0.5nsTh=0.5ns,Tsu,Th,Waveformoutputfromexternaldevice,216,DDRInputExample,Whatsdifferentaboutthiscircuitthanpriorexamples?Rising&fallingedgeinputregistersfromsameinputportRegistershaveclockperiodforrequiredtime,FPGA,datain,clk,Tclk=6ns,DVW,DVW,DVW,DVW,DVW,DVW,Tsu=0.5nsTh=0.5ns,Tsu,Th,Waveformoutputfromexternaldevice,217,DDRInputExample,create_clockperiod6get_portsclk#Risingedgeclockconstraintset_input_delayclockclkmaxexpr6/2-0.5datainset_input_delayclockclkmin0.5datain#Fallingclockedgeconstraintset_input_delayclockclkmaxexpr6/20.5datain-clock_falladd_delayset_input_delayclockclkmin0.5datain-clock_falladd_delay,FPGA,datain,clk,Tclk=6ns,DVW,DVW,DVW,DVW,DVW,DVW,Tsu,Th,Tsu=0.5nsTh=0.5ns,Waveformoutputfromexternaldevice,218,DDRReporting,Usereport_timingCommandMustcheckallrising&fallingedgetransitionsTwodatavalidwindowstocheckOnefromarisingedgesourceclockOnefromafallingedgesourceclockUserise_from,rise_to,fall_from,fall_to,219,PleasegotoExercise2,220,TimingAnalysisSummary,TimingconstraintsareveryimportantinFPGA/CPLDdesignUsetimingconstraintstotellfitter&timinganalyzerhowlogicisdesignedtofunctionSDCprovidesaneasy-to-use,standardinterfaceforconstrainingdesignSeetheQuartusIIHandbook:Volume3,SectionII,formoreinformationabouttiminganalysis,22