先进芯片封装知识介绍ppt课件

AdvancedPackagingTech,1,Outline,PackageDevelopmentTrend3DPackageWLCSP&FlipChipPackage,2,PackageDevelopmentTrend,3,SOFamily,QFPFamily,BGAFamily,PackageDevelopmentTrend,4,CSPFamily,MemoryCard,SiPModule,PackageDevelopmentTrend,5,3DPackage,3DPackage,3DPackageIntroduction,FunctionalIntegration,High,Low,2ChipStackWirebond,2ChipStackFlipChip&Wirebond,MultiChipStack,PackageonPackage(PoP)Stacking,PS-fcCSP+SCSP,PaperThin,PiP,PoPQFN,StackedDie,Topdie,Bottomdie,FOWmateril,Wire,TSV,TSV(ThroughSiliconVia)Athrough-siliconvia(TSV)isaverticalelectricalconnection(via)passingcompletelythroughasiliconwaferordie.TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits.A3Dpackage(SysteminPackage,ChipStackMCM,etc.)containstwoormorechips(integratedcircuits)stackedverticallysothattheyoccupylessspace.Inmost3Dpackages,thestackedchipsarewiredtogetheralongtheiredges.Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra“interposer”layerbetweenthechips.Insomenew3Dpackages,through-siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips.Theresultingpackagehasnoaddedlengthorthickness.,WireBondingStackedDie,WhatsPoP?PoPisPackageonPackageTopandbottompackagesaretestedseparatelybydevicemanufacturerorsubcon.,PoP,PoP,PS-vfBGA,PS-etCSP,LowLoopWire,PinGateMold,PackageStacking,WaferThinning,PoPCoreTechnology,PoP,Allowsforwarpagereductionbyutilizingfully-moldedstructureMorecompatiblewithsubstratethicknessreductionProvidesfinepitchtoppackageinterfacewiththrumoldviaImprovedboardlevelreliabilityLargerdiesize/packagesizeratioCompatiblewithflipchip,wirebond,orstackeddieconfigurationsCosteffectivecomparedtoalternativenextgenerationsolutions,AmkorsTMVPoP,PoP,BallPlacementontopsurface,BallPlacementonbottom,DieBond,Mold(UnderFulloptional),Laserdrilling,SingulationFinalVisualInspection,BaseMtl,Thermaleffect,ProcessFlowofTMVPoP,Digital(Btmdie)+Analog(Middledie)+Memory(Toppkg)PotableDigitalGadgetCellularPhone,DigitalStillCamera,PotableGameUnit,Memorydie,Analogdie,Digitaldie,spacer,Epoxy,PiP,14,EasysystemintegrationFlexiblememoryconfiguration100%memoryKGDThinnerpackagethanPOPHighIOinterconnectionthanPOPSmallfootprintinCSPformat,Ithasstandardballsizeandpitch,Constructedwith:FilmAdhesivedieattachEpoxypasteforTopPKGAuwirebondingforinterconnectionMoldencapsulation,WhyPiP?,PiP,15,MaterialforHighReliabilityBasedonLowWarpage,WaferThinning,FineProcessControlTopPackageAttachDieAttachetc,OptimizedPackageDesign,FlipChip,Under-fill,Topepoxy,ISM,PiPCoreTechnology,PiP,16,Analog,WBPIP,FCPIP,PiP,PiPW/BPiPandFCPiP,17,WLCSP&FlipChipPackage,WLCSP,WhatisWLCSP?WLCSP(WaferLevelChipScalePackaging),isnotsameastraditionalpackagingmethod(dicingpackagingtesting,packagesizeisatleast20%increasedcomparedtodiesize).WLCSPispackagingandtestingonwaferbase,anddicinglater.Sothepackagesizeisexactlysameasbarediesize.WLCSPcanmakeultrasmallpackagesize,andhighelectricalperformancebecauseoftheshortinterconnection.,19,WLCSP,WhyWLCSP?Smallestpackagesize:WLCSPhavethesmallestpackagesizeagainstdiesize.Soithaswidelyuseinmobiledevices.Highelectricalperformance:becauseoftheshortandthicktraceroutinginRDL,itgiveshighSIandreducedIRdrop.Highthermalperformance:sincethereisnoplasticorceramicmoldingcap,heatfromdiecaneasilyspreadout.Lowcost:noneedsubstrate,onlyonetimetesting.WLCSPsdisadvantageBecauseofthediesizeandpinpitchlimitation,IOquantityislimited(usuallylessthan50pins).BecauseoftheRDL,staggerIOisnotallowedforWLCSP.,20,RDL,RDL:RedistributionLayerAredistributionlayer(RDL)isasetoftracesbuiltuponawafersactivesurfacetore-routethebondpads.Thisisdonetoincreasethespacingbetweeneachinterconnection(bump).,WLCSP,ProcessFlowofWLCSP,22,WLCSP,ProcessFlowofWLCSP,23,FlipChipPackage,FCBGA(PassiveIntegratedFlipChipBGA),(PI)-EHS-FCBGA(PassiveIntegratedExposedHeatSinkFlipChipBGA),(PI)-EHS2-FCBGA(PassiveIntegratedExposed2piecesofHeatSinkFlipChipBGA),MCM-FCBGA(Multi-Chip-ModuleFCBGA),PI-EHS-MP-FCBGA(PassiveIntegratedExposedHeatSinkMultiPackageFlipChip),24,Bump,25,BumpDevelopment,BumpDevelopment,BumpDevelopment,C4FlipChip,WhatsC4FlipChip?C4is:ControlledCollapsedChipConnectionChipisconnectedtosubstratebyRDLandBumpBumpmaterialtype:solder,gold,C4FlipChipBGA,MainFeaturesBallPitch:0.4mm-1.27mmPackagesize:upto55mmx55mmSubstratelayer:4-16LayersBallCount:upto2912TargetMarket:CPU、FPGA、Processor、Chipset、Memory、Router、Switches、andDSPetc.,MainBenefitsReducedSignalInductanceReducedPower/GroundInductanceHigherSignalDensityDieShrink&ReducedPackageFootprintHighSpeedandHighthermalsupport,30,C2FlipChip,WhatsC2FlipChip?C2is:Ch