《FPGA功耗优化》PPT课件

PowerReductionTechniques,AlteraAsiaPacificRegionalSupportCenter,2,Agenda,IntroductionPower-DrivenSynthesisPower-DrivenFittingClockPowerManagementLow-PowerDesignConclusion,3,Introduction,67%,22%,11%,DynamicPowerDominantFocusofPowerOptimization,99CustomerDesignsonStratixIIDevices,4,DynamicPowerOptimizationFlow,Automatic,butlessaccurate,Requirestestbench,moreaccurate,EvaluatePower,RTL,Simulation,Power-DrivenFit,Design,PowerReport,Vectorless,Estimation,Hardware,Measurement,Gate-LevelSimulation,+PowerAnalyzer,EstimateToggleRates,Normal,or,Extraeffort,Power-Driven,Synthesis,5,Power-DrivenSynthesis,Locatedunder:“Analysis1kwords=deeper)MW“MaximumDepth”optionselectswider/shallowRAMsforpowere.g.4256x16blocks(x16=wider;256words=shallow)Accessonlyvalidmemoryslice,disabletherestDoesrequireadditionaldecoderandmuxlogichowever,8,RAMEnableOptimization,Convertread/writeenablestoclockread/writeenablesShutsRAMdownwhenunused,usinglesspowerSetRAMBlockType=“Auto”QuartusIIPowerOptimizerchoosesbestRAMblockconfiguration,9,MemoryBalancing,PowerEfficientOption,16,2:4Decoder,4256x16M4KRAMs,DefaultOption,16,41kx4M4KRAMs,1kx16RAM,10,MaximumDepthParameter,4kx36SimpleDual-PortmemoryimplementationusingM4KblocksFor128-deepM4Kmemoryblockdepth,extralogicpoweroutweighslowermemorypowerAverageDynamicPowersavingupto50%PowerPlayPowerAnalyzerresultsbasedonsimulation,M4KBlocksConfigurationwithDifferentMemoryDepthandWidth,PowerSaving,BestRange,11,Power-DrivenFitting,Locatedunder:“FitterSettings”,12,Power-DrivenFittingOptions,ExtraeffortOptimizesattheexpenseofspeedandcompiletimeGrouphigh-togglinglogictogethertominimizeroutingloadsGrouplogicfromsameclockdomainstominimizeclockroutingRunsPowerPlayPowerAnalyzerBestwithValueChargeDump(.VCD)orSignalActivity(.SAF)NormalcompilationOptimizeswithoutaffectingspeedorcompiletimeUsespowerefficientDSPblockconfigurationsbyswappinginputoperandorder(transparenttodesigner),13,MinimizeRoutingLoads,Minimizecapacitanceofhigh-togglingsignalsTimingconstraintsmaintained,14,MinimizeClockRouting,StandardPlaceelsereg=reg;end;,21,DynamicClockEnableforRAMs,RAMpowerprimarilyfromdynamicclockingPre-charge,dischargeofRAMarrayReducingnumberofclockeventsreducesdynamicpowerAddress/datainputshaveminimaleffectonpowerInternalmemorycircuitryactivewhetheraddressordatahaschangedUsememoryclockenablecontrolinMegaWizardCanobtainnearzerodynamicpoweroncycleswhenRAMnotaccessed,22,DynamicClockEnableinMegaWizard,23,Low-PowerDesign,Designtechniquesutilizespecificarchitecturefeatures,focusingonlowpowerTriMatrixmemoryoptimizedfordifferentRAMfunctionsQuartusIIcanselectbestsizeandconfigurationUsealtsyncramMegaFunctionDSPImplementationModeMultiplicationMultiply-AccumulationMultiply-AdditionLesspowerthanusingALM,24,Low-PowerDesignGlitchReduction,Somelogicproducesmanyedges/transitionspercycleE.g.CRC/parity,combinationalmultipliersEachtransition,orglitch,resultsinunnecessarypowerconsumptionRegisterinputs&outputsoftofilterout“glitchy”behaviorInsertpipelineregistersifpossible,Downstream,Logic,D,Q,25,Low-PowerDesignPipelining,EffectiveforglitchpronearithmeticsystemsAdvantagesIncreasedspeedShortlogicdepthReducedswitching(lessdynamicpower)DisadvantagesIncreasedlogicandregisterutilizationMayincreasepowerfordesignswithminimalglitchesLatencyandthroughputchanged,26,PowerOptimizationAdvisor,ExplainspoweranalysisbestpracticesProvidesOptimizationsuggestionsHighlightsrecommendedsettingsnotenabledindesign,27,DesignSpaceExplorer,SearchesQuartusoptionstofindbestimplementation“SearchforLowestPower”Findssettingsthatminimizepowerwhilemeetingtimingconstraints“quartus_shdse”,orToolsMenu,28,Conclusion,PowerreductionisamajorpartofsuccessfulFPGAdesignQuartusIIsoftwareprovidesoptionstoreducepowerPower-DrivenSynthesisPower-DrivenFit