EDA用VHDL语言设计一个2-4译码器

2-4译码器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY decoder 2 _4 ISPORT( a:IN STD_LOGIC_VECTOR(1 DOWNTO 0); s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END decoder2_4;ARCHITECTURE Behavioral OF decoder2 _4_t ISBEGINPROCESS(sel)BEGINCASE a ISWHEN 00=ssssssssss=ZEND CASE;END PROCESS;END Brhavioral; 100进制加法计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY counter IS PORT(clk,en,load,rst:IN STD_LOGIC d;IN STD_LOGIC_VECTOR(6 DOWNTO 0); q: OUT STD_LOGIC_VECTOR(6DOWNTO 0):END counter 100;ARCHTECTURE Behavioral OF counter 100 ISsignal qtemp:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGINPROCESS(clk,d,en,load,rst)BEGIN IF rst= 1 THEN qtemp=”00000000”; ELSIF rising-edge(clk) THEN IF en=1 THEN IF load=1 THEN qtemp=d, ELSIF qtemp=”1100011” THEN qtemp=”00000000”; ELSIF qtemp=qtemp+1; END IF; END IF;END IF; END PROCESS;q=qtemp;END Behavioral;8位从高至低串入串出移位寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY shift.register ISPORT( d,clk:IN STD_LOGIC; q:OUT STD_LOGIC);END d shift.register;ARCHITECTURE Behavioral OF shift.register ISsignal qtemp:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINPROCESS(d,clk)BEGIN IF rising-edge(clk) THEN q=dtemp(0); dtemp=d&dtemp(7 DOWNTO 1); END IF;END PROCESS;END Behavioral;状态机LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY fsm IS PORT(tin,clk:IN STD_LOGIC; yout:OUT STD_LOGIC_VECTOR(1DOWNTO 0);END fsm;ARCHITECTURE Behavioral OF fsm ISTYPE state-type IS (S0,S1,S2)signal state,next_state:state_type;BEGINSYNC_PROC:PROCESS(clk) BEGIN IF rising_edge(clk) THEN state yout yout youtyout=”zz”;END LAST; END PROCESS;NEXT_STATE_DECODE:PROCESS(state,tin) BEGIN next_statenext_state next_state IF