后端设计PPT演示课件

第十二章,后端设计,Outlines,BackendDesignFlowFloorplanPlaceminimalspacingtodigitalblock;IOlocationDiesizeissuePinlimited;CorelimitedPower-GroundroutingissuePowerringwidthaccordingtopoweranalysisPowerstrip/meshspacingPinplacementandIOringissue(willbetalkedinnextclass)Padpitchvs.boundingrule;ESD;noiseisolation;,DieSizeIssuecont.,Determinetheareaforstandardcells“Utilization”70%?80%?90%?ExtraspaceforclktreesynthesisExtraspaceforscanchainLayersforrouting,HardMacroPlacement,MacrosaregenerallyplacedaroundtheperipheralI/OringAcontiguousareaforstandardcells.Higherfreedomforyourplace-and-routetoolsduringplacementandroutingofthestandardcellsThegoalofmacroplacementisto:Reducetiming-criticalpathsbetweenthemacrosandinterfacinglogic.Reduceinterconnectionsinthefollowingorder:ChipI/OtomacrosMacrotomacroMacrotostandardcellblocks,Power/GroundDevelopment,IRDropandElectromigrationPower-netIRdropdegradesthesupplyvoltagelevelExcessivecurrentdensityinmetalwirecauseselectromigrationfailurewhichbreaksmetalconnectionMoresignificantIRdropeffectwhenVddgetssmallerHighercurrentdensitywhenmetalwirewidthissmaller,Power/GroundDevelopment-cont.,RingstructurePowerringsaroundalllayoutblocksMajorpowertrunksbetweenlayoutblocksDifficulttoguaranteetheworstIRdropStrapstructureSimple,easyforroutingMeshstructureEvenlydistributeofIRSpacingofPowerstripsconsiderationIRdropanalysisFixtheprobleminearlystage,P/GStructures,BeWareofMaximumWidthRule,MaximumwirewidthlimitduetothermalstressandlocaldensityrulesSlottingvs.“bus”ofthinwiresDisadvantageofslotting:SlotsmaynotbealignedwithcurrentflowTrueIRdropnotknownuntilafterslottingEspecialhappenforPower/Groundrings,Commonlyusedforpower/ground,Placement,Basedonagivenfloorplan,determinethelocationofcellsinagivennetlistGoals&objectivesRoutabilityGuaranteetheroutercancompletetheroutingstep(Globalrouting)TimingMinimizeallcriticalnetdelaysMinimizediesizeMakethechipasdenseaspossibleSignalIntegrity,CheckfeasibilityofroutingafterplacementLogiceffort-forthosepathswithpositiveslack,reducecellsize,CongestionandFix,Before,After,Congestionareas,Routing,Completepower/ground/clockrouting(clocktreesynthesis)Completedetailedwirerouting,conformwiringruleandorder)ImprovethedensityMinimizethelayerchangesImprovecriticalpathandmeettimingrequirementProducearouteddesignfreeofDRC/LVSviolations,GeneralRoutingFlow,ClockTreeSynthesisAddbuffers/inverters,minimizeclkskewanddelayPostPlacementOptimization(PPO)FixsetupviolationPre-RouteStandardCellsVDD/VSSrailsonmetal1VerifyPGconnectionandroutingRouteGroupNetclocksbusroutingPost-RouteCTOFixclkskewandinsertiondelayGlobalRoutingcriticalpathlongwire,interconnection,Routingflowcont.,TrackAssignment&DetailRoutingWireconnectionSearch&Repair(DRC/LVS)fixroutingviolation(unconnectednets,shorts)PostRouteOptimizationFixtimingCoarseLVS&DRCcheckingmetalwidth,notch&gapcheckingDataOutputstreamout:gds2formatverilogout:hierarchy(PT)/non-hierarchy(forHercules)parasiticout:spefformat(cellview),ClockTreeSynthesis,Objective:minimizeclockskewoptimizeclockbuffers,BasicCTSFlow&Concepts,ClockConstraint,Define:Clksource:rootpin,targetinsertiondelay,targettransitiontimeatclkportClkendpoint:Synchronouspin,ignore/excludepinDrivingcell,clkcell,delaycell:buffers,inverters,specialclkcellsDRC:maximumtransitiondelay,maximumnetcapacitance,maximumfanout,clknumberofbufferlevels,ClockSkew,GlobalSkewandLocalSkewGlobalskewGlobalskewistheclockarrivaltimedifferencebetweenanytwoflip-flops.LocalskewLocalskewistheclockarrivaltimedifferencebetweentwoflip-flopsthatareadjacentthroughcombinationallogic.,ConceptofUsefulSkew,Usefulskewisamethodofintentionallyskewingaclocktoimprovethetimingonacircuit.ItisalsocommonlyusedinECO,Warning:CouldcauseprobleminDFTscaninsertion,UseCTSforHigh-FanoutNetSynthesis,High-fanoutpins:rest,scan_enNeedtobalancehigh-fanoutpinstoguaranteethefunctionalityUsingCTStool:high-fanoutnetsbyinsertingabalancedbuffertreeTominimizebothskewandinsertiondelayButshouldavoidusinglargebuffersforpowersaving,LargeSoCClockDistribution,PartitionthedesigntoseveralblocksCTSforeachblockClktreenetworkattoplevel,Externalclock,CoreInternalClockNet,GlobalClockNet,HTreeforTopClockNetwork,UsebigbuffertobalancedelayandclkskewEqualdistance,equalloads,equaldrivingability,ClockDistributionCaseStudy:PentiumSpines,Kurdetal.,AmultigigahertzclockingschemeforthePentium4microprocessor,JSSC2001,ClockDistributionCaseStudy:IntelsItaniumHTreeClocking,Tametal.,ClockgenerationanddistributionforthefirstIA-64microprocessor,JSSC2000,Issues,LargeamountofclockbuffersaddedonclocktreePowerconsumptionNoisetosupplylinesReducepowerconsumptionWidewirewidthsClockgatingcellplacementLimitationofusinglargeclockbuffercellsReducenoiseSpecialclockbuffercellswithdecouplingcapacitor,Extraction,WhencompletedetailedrouteWriteoutthehierarchicalnetlistandparasiticforbackannotationDatamanagementonhugefileofextractedparasiticdataAccurateRCandtimingmodelfornanometerdesignWidthandspacingdependenceResistanceshieldingLocaldensityeffect,SDFBackAnnotation,Usedincell-baseddesignflowPerformsdelaycalculationonparasiticRCsininterconnectwiresDSPF-DetailedStandardParasiticFormatSPEFStandardParasiticexchangeFormatSDF-StandardDelayFormatusedforpost-layoutsimulationCanbeconvertfromPrimeTime,PhysicalVerification,DRC-DesignRulecheckVerifythemanufacturingrules,example:InternallayerchecksWidemetalchecksMetalslottingneededforwidemetalLayer-to-layerchecksDFM/DFYExample:AntennaRuleCheckLVSLayoutvs.SchematicsComparelayouttoschematics-everycellandnet,DRCTrendsandChallenge,75%timeonmetallayerandviacheckERC-typechecksincreasingRiseofpre-tapeoutDFMutilities,LVS,Layoutvs.Schematic(LVS)CheckphysicallayoutagainstfunctionalgatelevelschematictoensureallintendedconnectivityhasbeenmaintainedSteps:Extractthenetlistfromlayout(GDSII)ComparethenetlistwiththeoneafterroutingandoptimizationHints:MostofLVSerrorsarecausedbymanuallayoutorcongestion“Virtualconnect”(connectedbytext)couldcauseakillerfailure,SignalIntegrity,SignalIntegrityistheabilityofasignaltogeneratecorrectresponseinacircuitSignalhasdigitallevelsatappropriateandrequiredvoltagelevelsatrequiredinstantsoftimeCrosstalk,IRDrop,Electromigration,LayoutParasiticvs.CircuitPerformance,Interconnectparasiticresistors,capacitorsandinductorscauseextratimingdelayAdditionalpowerconsumptioncausedbyparasiticRCInter-wirecapacitancescausecouplingnoiseandwilldominateinterconnectwiredelaysParasiticresistancesinpowersupplycausevoltagedropandmaydegradecircuitperformanceHighercurrentdensityinpowernetmaycauseelectromigrationfailure,InductanceEffects,InductivecouplingeffectissignificantforlonginterconnectsandforveryfastsignaledgerateInductivecouplingisnegligibleatshorttraceinterconnects,sincetheedgetraceislongcomparedtotheflighttimeofthesignalInductanceextractionandsimulationaremoredifficultthancapacitance,C,L,CrosstalkAnalysis,DefinitionAggressor:generatingcrosstalkVictim:receivingcrosstalkTimingsensitiveCrosstalkanalysisconsistingsignaltransitiontimingwindowcaneliminatepessimisticdelaycalculationThecrosstalkspikeisrelatedtocapacitancevalueandthevictimdriverimpedance,CrosstalkAnalysiscont.,Timingsensitive,CrosstalkPrevention,PreventcrosstalkfromsynthesisstageMinimizethedrivingsizeonthosenon-criticalpathtoreducethenumberofaggressorsApplymaxtransitiontime(set_max_transition)inphysicalsynthesis/placementtoavoidlongnets,CrosstalkPreventioncont.,FromroutingstageEffectivespacingbetweennoiseregionandquiteregionShieldingbetweencriticalpaths,CrosstalkPreventioncont.,Fromroutingstagecont.BufferinsertionInsertedbufferbreaksupthecouplingcapacitanceoflongwire,CrosstalkPreventioncont.,Fromroutingstagecont.BuffersizingIncreasethedriversizeofvictimDecreasethedriversizeofaggressorTrackreorderingTrackreorderingisbasedontimingwindow,CrosstalkPreventioncont.,ForinductancecrosstalkCoplanarShieldsReferencePlanStaggerInverter/Buffer,ElectromigrationEffects,Theelectronsflowthroughthewiresandcollidew/metalatoms,producingaforcethatcausesthewirestobreakCausedbythehighcurrentdensitiesandhighfrequenciesgoingthroughthelong,verythinmetalwiresMTTF(MeanTimeToFailure)increaseswhencurrentdensityandtemperatureincreaseCanbeeliminatedbyusingtheappropriatewiresizing,FixEM,ControllingcurrentdensitytolimitelectromigrationfailureisneededindesignandverificationLayoutoptimization:Increasethepowerlinewidth,layerIncreasethepowerpadsIncreasetheconnectionIssuesMoremetal(add8%costperlayer)Larger,slowerdesigns(growinxandy),OtherConsiderations,ESD(willbetalkedinnextclass)Packagevs.performance(willbetalkedinnextclass)DFM/DFY,DFM/DFY,90nmandbelowtechnologieschallengesinyieldDFMDesignforManufacturabilityDFYDesignforYield,DFMandDFY,DFMisthemanagementoftechnologyconstraints(sizingrules)appliedtothelayoutAmanufacturabledesignhoweverisnotnecessarilyahigh-robustorhigh-yieldingdesign.DFY,aspartofDesignforManufacturability,concentratesonthedevelopmentandqualityofthecircuitdesigninthepre-andpost-layoutphase.DFYisthemanagementofdesignsensitivitiestothemanufacturingprocessandhelpstoguaranteehigh-yieldingdevices,DFM/DFYMethodology,Optimalresolutionenhancementtechnology(RET)MaskandexposureOpticalProximitycorrection(OPC)PhaseShaftMask(PSM)YieldenhancementandoptimizationtechnologyDFMrulesimplementationToovercomelimitsofOPCYieldcheckingduringthelayoutstageSupportedbyEDAtools,WhyNeedRET?,Wavelengthusedvsprocessgeneration,DesignforManufacturing,Notallthethingscanbedonebymaskandexposure:CorrectionsarenotcompleteSomedesignscannotbebuiltatallwithcertainRETtechnologiesOfthosethatCANbebuilt,somearemoremanufacturableafterRETthanothersDFM/DFY-drivenroutingOPC-drivenroutingPSC-drivenplacementDFMruleimplementation,DFM/YRules,Limittheuseofminimalpoly-enclosedgates,minimallyenclosedviasandsinglycontactedlinesBetteryieldLessresistanceExample:ViaVoidrules-doubledvias,CurrentDFM/YDesignFlowSupported,LoadDesign,Performantennafixes,Addcontacts/via,MetalFill&Slotting,VerifyLVSandDRC,WhyNeedDoubleVias?,CopperprocessingcausesnewproblemsforviasVoidsinCumigrateunderthermalstresstowardsviasIfenoughvoidsmigratetoaviaitcancausefailureWorseat90/65nmduetoincreasedstressofsmallervia,Voidscanmigratelongdistances10microns,Voidscanmigratearoundcorners,Yieldvs.Area,AntennaRules,AntennaruleshavenothingtodowithtraditionaldefinitionofantennaReallyacollectorofstaticcharge,notelectromagneticradiationAntennaproblemonlyhappensduringmanufacturingPlasma-basedprocessforetching,oxidedepositionPlasmaetcherincludeavoltageintofloatingwire,stressingthethingate-oxidesNotanewpr