SAP-1 Cpu 电路设计.ppt

SAP-1Cpu电路设计,一.SAP-1CPU及计算机的组成架构简介二.SAP-1CPU指令.寻址法.三.16*8的ROM设计与仿真四.SAP-1CPU设计与仿真,实验目的：,实验原理,小组成员,薛宝（20054440118）汪威（20054440119）高亮（20054440120）吴安乐（2005444021）陆仁聪（20054440122）谢素斌（20054440123）吴运兴（20054440124）江宪清（20054440126）,一.SAP-1CPU及计算机的组成架构简介,所有寄存器是以三态(threestate)输出方式，连接至webus上。虽然现在不是使用传统TTL电路组成，而是使用CPLD-statetypedeclareSIGNALPState:STATE;-presentstateSIGNALNState:STATE;-nextstateBEGIN.*ChangeStateMode:PROCESS(CR,RST)-states0s5BEGINIFRST=1THEN-resetcpuPC=“0000”;-pogramcounter=0HACC=“00000000”;-accumulator=0HRUN=1;-CPUrunprogramenablePState-(addressstate,2.编写“指令捕捉周期（fetchcycle)即状态S0S2的命令,Changestatemode:process(cp,rst)-states0s5variableflag,f1:boolean;beginifrst=1then.PstatenstatenstateWhens3=nstate,其余指令执行周期的命令，不放入CASEWHEN语句里，而改以IF-ELSE将状态S3S5命令独立出来，这么作只是不希望CASEWHEN语句太过冗长。changestatemode:process(cp,rst)variableflag,F1:boolean;BeginIfrst=1thenElsifcpeventandcp=0thenIfrun=1thencasepstateiswhens0=nstate=s1;endcase;pstate=nstate;Endif;,Ifpstate=s3thenIf(tmp=“0000”)or(tmp=“0001”)or(tmp=“0010”)thenMar=ir(3downto0);elsiftmp=“1110”thenoutreg=acc;elsiftmp=“1111”thenrun=0;EndifElsifpstate=s4theniftmp=“0000”thenacc=databus;elsiftmp=“0001”thenbreg=databus;elsiftmp=“0010”thenbreg=databus;endif;Elsifpstate=s5theniftmp=“0001”andf1=turethenNum=unsigned(acc)+unsigend(breg);,Acc=std_logic_vector(num);F1:=false;Elsiftmp=“0010”andf1=truethennum=unsigned(acc)-unsigned(breg);Acc=std_lo