系统结构实验报告二

计算机系统结构课内实验实验报告班级：计算机01姓名：陈世阳学号：日期：2013.5.17一、实验目的及要求1. 加深对Cache的基本概念、基本组织结构以及基本工作原理的理解；2. 了解Cache的容量、相联度、块大小对Cache性能的影响；3. 掌握降低Cache失效率的各种方法，以及这些方法对Cache性能提高的好处；4. 理解Cache失效的产生原因以及Cache的三种失效；5. 理解LRU与随机法的基本思想，及它们对Cache性能的影响；二、实验环境redhat虚拟机下SimpleScalar模拟器三、实验内容1. 运行SimpleScalar模拟器；2. 在基本配置情况下运行程序（请指明所选的测试程序），统计Cache总失效次数、三种不同种类的失效次数；3. 改变Cache容量（*2，*4，*8，*64），运行程序（指明所选的测试程序），统计各种失效的次数，并分析Cache容量对Cache性能的影响；4. 改变Cache的相联度（1路，2路，4路，8路，64路），运行程序（指明所选的测试程序），统计各种失效的次数，并分析相联度对Cache性能的影响；5. 改变Cache块大小（*2，*4，*8，*64），运行程序（指明所选的测试程序），统计各种失效的次数，并分析Cache块大小对Cache性能的影响；6. 分别采用LRU与随机法，在不同的Cache容量、不同的相联度下，运行程序（指明所选的测试程序）统计Cache总失效次数，计算失效率。分析不同的替换算法对Cache性能的影响。四、实验步骤1.启动虚拟机，载入redhat操作系统2.进入 cd /roott/simplesacalar/ 目录3. 继续进入simplesim-3.0 目录：rootlocalhost simplesacalar# cd simplesim-3.0/4. 在当前目录下执行如下指令：rootlocalhost simplesim-3.0# ./sim-cache -cache:dl1 dl1:256:32:2:1 ./tests-pisa/bin.little/test-math其中dl1 指定cache, 256表示组数，32表示块大小，2表示相联度，l表示替换算法。组数，块大小，相联度都可以按需要进行设置。替换算法中，l表示LRU替换算法，r表示随机替换算法，f表示先进先出替换算法。5. 改变步骤4中命令的4个参数，记录实验结果。6. 修改命令如下：-cache:dl1 dl1:256:32:2:l # l1 data cache config, /一级数据cache-cache:dl2 ul2:1024:64:4:l # l2 data cache config,/ 二级数据cache-cache:il1 il1:256:32:1:l # l1 inst cache config, /一级指令cache-cache:il2 dl2 # l2 instruction cache config, /二级指令cache-tlb:itlb itlb:16:4096:4:l # instruction TLB config, /指令快表-tlb:dtlb dtlb:32:4096:4:l # data TLB config, /数据快表我们在实验中主要关注的是一级数据cache的性能变化，因此在以下的实验结果中，只展示出一级数据cache的相关指标。五、实验结果执行一次指令后的结果格式如下：执行的指令：rootlocalhost simplesim-3.0# ./sim-cache -cache:dl1 dl1:256:32:2:1 ./tests-pisa/bin.little/test-mathsim: * simulation statistics *sim_num_insn # total number of instructions executedsim_num_refs 56902 # total number of loads and stores executedsim_elapsed_time 1 # total simulation time in secondssim_inst_rate .0000 # simulation speed (in insts/sec)il1.accesses # total number of accessesil1.hits # total number of hitsil1.misses 23763 # total number of missesil1.replacements 23507 # total number of replacementsil1.writebacks 0 # total number of writebacksil1.invalidations 0 # total number of invalidationsil1.miss_rate 0.1112 # miss rate (i.e., misses/ref)il1.repl_rate 0.1100 # replacement rate (i.e., repls/ref)il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref)il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)dl1.accesses 57483 # total number of accessesdl1.hits 56925 # total number of hitsdl1.misses 558 # total number of missesdl1.replacements 124 # total number of replacementsdl1.writebacks 113 # total number of writebacksdl1.invalidations 0 # total number of invalidationsdl1.miss_rate 0.0097 # miss rate (i.e., misses/ref)dl1.repl_rate 0.0022 # replacement rate (i.e., repls/ref)dl1.wb_rate 0.0020 # writeback rate (i.e., wrbks/ref)dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)ul2.accesses 24434 # total number of accessesul2.hits 23230 # total number of hitsul2.misses 1204 # total number of missesul2.replacements 0 # total number of replacementsul2.writebacks 0 # total number of writebacksul2.invalidations 0 # total number of invalidationsul2.miss_rate 0.0493 # miss rate (i.e., misses/ref)ul2.repl_rate 0.0000 # replacement rate (i.e., repls/ref)ul2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref)ul2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)itlb.accesses # total number of accessesitlb.hits # total number of hitsitlb.misses 23 # total number of missesitlb.replacements 0 # total number of replacementsitlb.writebacks 0 # total number of writebacksitlb.invalidations 0 # total number of invalidationsitlb.miss_rate 0.0001 # miss rate (i.e., misses/ref)itlb.repl_rate 0.0000 # replacement rate (i.e., repls/ref)itlb.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref)itlb.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)dtlb.accesses 57483 # total number of accessesdtlb.hits 57473 # total number of hitsdtlb.misses 10 # total number of missesdtlb.replacements 0 # total number of replacementsdtlb.writebacks 0 # total number of writebacksdtlb.invalidations 0 # total number of invalidationsdtlb.miss_rate 0.0002 # miss rate (i.e., misses/ref)dtlb.repl_rate 0.0000 # replacement rate (i.e., repls/ref)dtlb.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref)dtlb.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)ld_text_base 0x # program text (code) segment baseld_text_size 91744 # program text (code) size in bytesld_data_base 0x # program initialized data segment baseld_data_size 13028 # program inited .data and uninited .bss size in bytesld_stack_base 0x7fffc000 # program stack segment base (highest address in stack)ld_stack_size 16384 # program initial stack sizeld_prog_entry 0x # program entry point (initial PC)ld_environ_base 0x7fff8000 # program environment base address addressld_target_big_endian 0 # target executable endian-ness, non-zero if big endianmem.page_count 33 # total number of pages allocatedmem.page_mem 132k # total size of memory pages allocatedmem.ptab_misses 34 # total first level page table missesmem.ptab_accesses # total page table accessesmem.ptab_miss_rate 0.0000 # first level page table miss rate我们主要关注上述结果中粗体及下划线的部分性能指标。以下的性能比较即以上述指标为依据。5.1cache容量不变，改变块大小和组数。实验结果如下表1：cache容量=16384，相联度为2，置换算法LRU表1组数块大小总访问数命中数命中率替换率12812857483570210.99200.00012566457483571860.99480.00015123257483569410.99060.000110241657483564700.98240.0001分析结果：从表中可以看出，组数为256，块大小为64时，cache的命中率最高。增大组数或者增大块大小后，cache的性能都有所下降。故cache容量一定时，并不是一味地增大块大小或一味地提高组数就可以提高命中率，需要再块大小和组数这两个参数上面做个均衡。通过实验来得出最佳搭配。5.2块大小和组数不变，改变相联度，实验结果如下表2：组数:256;块大小：32;置换算法：LRU表2相联度总访问数命中数命中率替换率257483569250.99030.002