东南大学CPU报告

止于至善Micro-programmed CPU ReportCOA Course DesigncontentsPurpose2Experiment Principle2Instruction Set2Internal Registers and Memory3MAR (Memory Address Register)3MBR (Memory Buffer Register)4PC (Program Counter)4IR (Instruction Register)4ACC (Accumulator)5MR (Multiplier Register)5DR (Division Register)5LPM_RAM_DQ5ALU (Arithmetic Logic Unit)6Micro-programmed Control Unit6CPU Architecture8Control signals in Control Memory8Contents of Control Memory9Top level circuit diagram11Simulation results:12Problem 1: Calculate the sum of all integers from 1 to 10012Problem 2: Calculate 300 and 27514Results Analysis14Further Improvement15Reference15Appendix151MBR module152BR module163ALU module174IR module185PC module196MAR module207control_unit module218MR module22PurposeThe purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need to consider the following items: Read/Write Registers, Read/Write Memory and execute the instructions. At least four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set, which are the main aspects of our project design and will be studied.Experiment PrincipleInstruction SetSingle-address instruction format is used in our simple CPU design. The instruction word contains two sections: the operation code (opcode), which defines the function of instructions (addition, subtraction, logic operations, etc.); the address part, in most instructions, the address part contains the memory location of the datum to be operated, we called it direct addressing. In some instructions, the address part is the operand, which is called immediate addressing. For simplicity, the size of memory is 25616 in the computer. The instruction word has 16 bits. The opcode part has 8 bits and address part has 8 bits. The instruction word format can be expressed in Figure 1OPCODE15:8ADDRESS7:0Figure 1 the instruction formatThe opcode of the relevant instructions are listed in Table 1. In Table 1, the notation x represents the contents of the location x in the memory. For example, the instruction word (03B916) means that the CPU adds word at location B916 in memory into the accumulator (ACC); the instruction word () means if the sign bit of the ACC (ACC 15) is 0, the CPU will use the address part of the instruction as the address of next instruction, if the sign bit is 1, the CPU will increase the program counter (PC) and use its contentInternal Registers and Memory MAR (Memory Address Register) MAR contains the memory location of the word to be read from the memory or written into the memory. Here, READ operation is denoted as the CPU reads from memory, and WRITE operation is denoted as the CPU writes to memory. In our design, MAR has 8 bits to access one of 256 addresses of the memory. In my experiment, the MAR block is as figure 2Figure 2MBR (Memory Buffer Register) MBR contains the value to be stored in memory or the last value read from memory. MBR is connected to the address lines of the system bus. In our design, MBR has 16 bits. In my experiment, the MBR block is as figure 3Figure 3PC (Program Counter) PC keeps track of the instructions to be used in the program. In our design, PC has 8 bits. In my experiment, the PC block is as figure 4Figure 4IR (Instruction Register) IR contains the opcode part of an instruction. In our design, IR has 8 bits. BR (Buffer Register) BR is used as an input of ALU, it holds other operand for ALU. In our design, BR has 16 bits. In my experiment, the Instruction register is as figure 5Figure 5ACC (Accumulator) ACC holds one operand for ALU, and generally ACC holds the calculation result of ALU. In our design, ACC has 16 bits. MR (Multiplier Register) MR is used for implementing the MPY instruction, holding the multiplier at the beginning of the instruction. When the instruction is executed, it holds part of the product. In my experiment, the MR is as figure 6Figure 6DR (Division Register) DR is used for implementing the DIV instruction, you can define it according to your division algorithm. Its optional. Here, we ignore it.LPM_RAM_DQ LPM_RAM_DQ is a RAM with separate input and output ports, it works as memory, and its size is 25616. Although its not an internal register of CPU, we need it to simulate and test the performance of CPU. All the registers are positive-edge-triggered. All the reset signals for the registers are ALU .Figure 7ALU (Arithmetic Logic Unit) ALU is a calculation unit which accomplishes basic arithmetic and logic operations. In our design, some operations must be supported which are listed as follows e synchronized to the clock signal.In my experiment, the ALU block is as figure 8Figure 8Table 2 ALU operationsMicro-programmed Control Unit We have learnt the knowledge of Micro-programmed control unit. Here, we only review some terms and basic structures. In the Micro-programmed control, the micro-program consists of some microinstructions and the micro-program is stored in control memory that generates all the control signals required to execute the instruction set correctly. The microinstruction contains some micro-operations which are executed at the same time.Microinstructions are stored in the control memory. The control address register contains the address of the next microinstructions to be read. When a microinstruction is read from the control memory, it is transferred to a control buffer register. The register connects to the control lines emanating from the control unit. Thus, reading a microinstruction from the control memory is the same as executing that microinstruction. The third element shown in the figure 9 is a sequencing unit that loads the control address register and issues a read command.Instruction registerControl SignalsControl Buffer RegisterControl MemoryCAR (control address Register)Sequencing logicFigure 9 Control UnitIn my CPU, the control address is defined as a variable, without a single part. The control unit is as figure 10.And the control memory is as figure 11.Figure 10Figure 11CPU Architecture Figure 12Control signals in Control MemoryTable 3 Control SignalsBit in read-only control memory (Bit of ROM)Micro-operationControl signal nameC0CARCAR+1Increase CARC1CAR*Control addressingC2CAR0Reset CARC3MBRmemoryRead RAMC4IRopcodeMBR(15.8)MBR into IRopcodeC5MARMBR7.0MBR into MARC6PCPC+1Increase PCC7BRMBRMBR into BRC8ACC0reset_ACCC9ACCACC+BRADDC10MARPCPC into MARC11memoryMBRRAM _writeC12MBRACCACC into MBRC14PCMBRMBR into PCC15PC0Reset_PCC16ACCACC-BRSUBC17Shift ACC to rightSHIFTRC18MRACC*BR（H）MPY(H) into MRC24ACCACC*BRMpy(L)C25Shift ACC to leftSHIFTLC26ACCNOT ACCNOTC27ACCACC or BROR C28 ACCACC and BRANDContents of Control MemoryTable 4 Contents of control memoryAddress(Hex)Micro-instructionsControl Signals0 (FETCH)MBRmemory，CARCAR+1C3,C0 1IRopcodeMBR15-8，CARCAR+1C4,C0 2CAR*C1 10 (LOAD)MARMBR7-0,PCPC+1,CARCAR+1C5,C6,C0 11MBRmemory , CARCAR+1C3,C0 12ACC0, BRMBR, CARCAR+1C8,C7,C0 13ACCACC+BR, CARCAR+1C9,C0 14MARPC, CAR0C10,C2 20(STORE)MARMBR7-0,PCPC+1,CARCAR+1C5,C6,C0 21MBRACC, CARCAR+1C12,C0 22memoryMBR, CARCAR+1C11,C0 23MARPC，CAR0C10,C2 30(ADD)MARMBR7-0, PCPC+1, CARCAR+1C5,C6,C0 31MBRmemory, CARCAR+1C3,C0 32BRMBR, CARCAR+1C7,C0 33ACCACC+BR, CARCAR+1C9,C0 34MARPC, CAR0C10,C2 40 (SUB)MARMBR7-0, PCPC+1, CARCAR+1C5,C6,C0 41MBRmemory, CARCAR+1C3,C0 42BRMBR, CARCAR+1C7,C0 43ACCACC-BR, CARCAR+1C16,C0 44MARPC, CAR0C10,C2 50(HALT)ACC0, CAR0 ,PC0C8,C15,C2 60(AND)MARMBR7-0, PCPC+1, CARCAR+1C5,C6,C0 61MBRmemory, CARCAR+1C3,C0 62BRMBR, CARCAR+1C7,C0 63ACCACC and BR, CARCAR+1C28,C0 64MARPC，CAR0C10,C2 70(OR)MARMBR7-0 ,PCPC+1, CARCAR+1C5,C6,C0 71MBRmemory, CARCAR+1C3,C0 72BRMBR, CARCAR+1C7,C0 73ACCACC or BR, CARCAR+1C27,C0 74MARPC, CAR0C10,C2 80(NOT)MARMBR7-0 ,PCPC+1, CARCAR+1C5,C6,C0 81MBRmemory, CARCAR+1C3,C0 82BRMBR, CARCAR+1C7,C0 83ACCnot ACC, CARCAR+1C26,C0 84MARPC, CAR0C10,C2 90(SHIFTR)ACCACC1, PCPC+1,CARCAR+1C17,C6,C0 91MARPC, CAR0C10,C2 A0(SHIFTL)ACCACC=0 goto loop;end2.Assume in the memory: sum is stored at location A4, temp is stored at location A3, the contents of location A0 is 0, the contents of location A1 is 1,the contents of location A2 is 10010=6416.We can translate the above C language program with the instructions listed in Table 1 into the instruction program as shown in Table 4.Table 5 Example of a program to sum from 1 to 100Program with CProgram with instructionsContents of Memory (RAM) in HEXAddressContentssum=0;LOAD A00002A0STORE A40101A4temp=100;LOAD A20202A2STORE A30301A3loop :sum=sum+temp;LOOP:LOAD A404 (so LOOP=04)02A4ADD A30503A3STORE A40601A4temp=temp-1;LOAD A30702A3SUB A10804A1STORE A30901A3if temp=0 goto loop;JMPGEZLOOP0A0504endHALT0BHALT.A00000A10001A20064Sum= sum +tempLOAD A4Temp= temp-1LOAD A3Final result:5050temp0,temp=-1Problem 2: Calculate 300 and 275LOAD A0 02A0TranslateAND A1 0AA1HALT 0700In the RAM, the address A0 has the content 300 and the A1 has the content 275.Load A0Final result: 256AND A1Results Analysis1. Problem 1: calculate the sum of all intergers from 1 to 100Through functional simulation, we get the waveform and the final summary is 100, which is correct. We also make the test for the function of the instruction LOAD, STORE, ADD, SUB, JMPGEZ etc.2. Problem 2: calculate 300 and 275Through functional simulation, we get the right answer, 256 and authenticate the instruction AND.3. Our simple CPU has implemented the basic function required.Further Improvement1. Instruction-level parallelism and superscalar is not implemented in our CPU, which will greatly improve the efficiency.2. Some complex instructions, such as DIV, are not implemented in the instruction set. Division can only be accomplished by shifting.3. Only direct addressing mode is realized. More modes, such as register addressing and indirect addressing can be designed in the future.4. There is no interrupt service provided in our simple CPU.5. In the real world, the speed of memory (RAM) is slowly than that of CPU. The ROM should share the same clock with CPU. In our simple CPU, the clock doesnt function perfectly. Further improvement must be made about this.Reference William, Stallings.“Computer Organization and Architecture, Designing for Performance”,Appendix1MBR modulelibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mbr isport(acc_in,memory_in:in std_logic_vector(15 downto 0);cs:in std_logic_vector(31 downto 0);clk:in std_logic;mbr_out:out std_logic_vector(15 downto 0);end mbr;architecture behave of mbr isbeginprocess(clk)beginif clkevent and clk=1then if cs(3)=1then mbr_out=memory_in; - MBRmemoryelsif cs(12)=1thenmbr_out=acc_in; - MBRACCend if;end if;end process;end behave;2BR module library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity br isport(mbr_in:in std_logic_vector(15 downto 0);cs:in std_logic_vector(31 downto 0);clk:in std_logic;br_out:out std_logic_vector(15 downto 0);end br;architecture behave of br isbeginprocess(clk)beginif clkevent and clk=1thenif cs(7)=1thenbr_out=mbr_in; - BRMBRend if;end if;end process;end behave;3ALU modulelibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity alu isport(br_in:in std_logic_vector(15 downto 0);cs:in std_logic_vector(31 downto 0);clk:in std_logic;accis0:out std_logic;acc:out std_logic_vector(15 downto 0);mpyhigh:out std_logic_vector(15 downto 0);end alu;architecture behave of alu issignal temp:std_logic_vector(15 downto 0);beginaccis0=1when temp(15)=1else0; -If ACC0,flag=1process(clk)variable x:std_logic_vector(31 downto 0);beginif clkevent and clk=1thenif cs(8)=1thentemp=00000; -resetelsif cs(9)=1thentemp=temp+br_in; -addelsif cs(16)=1thentemp=temp-br_in; -subelsif cs(17)=1thentemp=0&temp(15 downto 1); -shiftrelsif cs(24)=1then if (temp(15) xor br_in(15)=1thenif temp(15)=1 thenx:=(0-temp)*br_in;elsex:=temp*(0-br_in);end if;x:=0-x;temp=x(15 downto 0); mpyhigh=x(31 downto 16);elseif temp(15)=1 thenx:=(0-temp)*(0-br_in);elsex:=temp*br_in;end if;temp=x(15 downto 0); mpyhigh=x(31 downto 16);end if; -mpyelsif cs(25)=1thentemp=temp(14 downto 0)&0; -shiftlelsif cs(28)=1thentemp=temp and br_in; -andelsif cs(27)=1thentemp=temp or br_in; -orelsif cs(26)=1thentemp=not br_in; -notend if;acc=temp;end if;end process;end behave;4IR modulelibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ir isport(mbr_in:in std_logic_vector(7 downto 0); -mbr15.8cs:in std_logic_vector(31 downto 0);clk:in std_logic;ir_out:out std_logic_vector(7 downto 0);end ir;architecture behave of ir isbeginprocess(clk)beginif clkevent and clk=1then if cs(4)=1thenir_out=mbr_in;end if;end if;end process;end behave;5PC modulelibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity pc isport(mbr_in:in std_logic_vector(7 downto 0); -mbr15.8cs:in std_logic_vector(31 downto 0);clk:in std_