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Low Power 2:1 MUX for Barrel Shifter Prasad D Khandekar, Member IEEE, Assistant Professor-E 1. If charging time is greater than 2RC then the dissipated energy is smaller than that for conventional CMOS circuit. 2. Dissipated energy is inversely proportional to T, which means that dissipated energy can be made arbitrarily smaller by increasing the charging time. 3. Dissipated energy is proportional to R in contrast to conventional CMOS case wherein dissipated energy depends on load capacitor and voltage swing. 4. As charging resistance decreases, the energy dissipated decreases. Fig.2b depicts the charge flow in adiabatic circuit. Pull-up circuit drives the true output of the adiabatic gate while pull-down circuit drives the complementary output node. Both the networks in adiabatic charge up as well as charge down the output capacitor. At the end of the cycle, the energy flows back into the power supply. The important component in this circuit is the pulsed power supply with ramped voltage instead of a DC supply in conventional logic.2 Alternatively, a stepwise supply voltage can replace the ramped power supply where the output of a power supply varies in small steps during charging and discharging of a capacitor. The energy dissipated is proportional to average voltage drop traversed by the charge and it can be proved analytically that the total energy dissipated is inversely proportional to the total number of steps from logic 0 to logic 1 as explained in the section below. Experimental results showed that energy dissipation is 9.17 X10-13 J when inverter is charged by constant voltage whereas it is just 9.69 X 10-17 J when voltage is applied in three linear steps.3 3. Implementation of adiabatic logic 3.1 Design of adiabatic amplifier The fundamental concepts of adiabatic are experimentally proven with the help of adiabatic amplifier, which uses two CMOS transmission gates and two NMOS clamps, was discussed by William Athas et al 4. Figure 3a shows the adiabatic amplifier and its dual rail inputs and outputs. Figure 3a. Adiabatic Amplifier 405 Figure 3b. Energy-Recovery Principle The waveform of energy dissipation in the right pane of the fig 3b shows the energy being recovered after each cycle of input. 3.2. Design of 2:1 MUX Using Adiabatic Logic There are many ways to build a barrel shifter viz. Mux-based data reversal, Mask based data-reversal, Mask-based twos complement and Mask-based Ones complement. The study shows that Mux-based data reversal barrel shifter consumes less area than others and still gives better worst case delay. 5 Thus if adiabatic multiplexers are used in designing barrel shifter, the energy dissipation also can be minimized. Adiabatic techniques were used to reduce power consumption of 2:1 MUX6. Three adiabatic logic styles were selected Clocked CMOS Adiabatic) logic (CAL) 7, Pass Transistor Adiabatic Logic (PAL) 8 and Improved Pass Transistor Gate Logic (IPGL) 9. The designs were made using 180nm devices and functionally simulated in Cadence tool. The simulation results were compared with that of conventional CMOS 2:1 MUX. 4. Results and analysis All the designs were rigorously tested and effects of Vdd, frequency of operation i.e. select signal frequency, load capacitance on energy dissipation and delay were studied. Figure 4a shows the effect of Vdd on energy dissipation. PAL consumes the lowest energy and IPGL consumes the highest. Non-adiabatic energy losses are significant in IPGL as it uses more number of transistors. Energy dissipation in CMOS MUX is three times of PAL and almost same as CAL. Figure 4b shows the effect of select signal frequency on the energy dissipation. IPGL and PAL MUX dissipates very less amount of energy as compared to CAL. This is because CAL uses a sinusoidal power-clock supply and IPGL & PAL uses ramp type of power-clock supply. The energy dissipation is the highest in CMOS and is forty times that of IPGL and about three to five times that of PAL and CAL. Figure 4c shows the effect of load capacitance on energy dissipation. The load capacitance for CMOS Mux is 11.52fF for fan-out of 4. CAL and PAL dissipate very less energy as compared to CMOS i.e. 90% and 30% reduction in energy dissipation respectively. Figure 5a and 5b depict the effects of select signal frequency and load capacitance on delay respectively. All adiabatic logic circuits offer higher delays as compared to CMOS circuit but at higher frequencies CAL delays are comparable with CMOS. Adiabatic delays are about twenty to thirty times that of CMOS delays at frequencies greater than 60 MHz. The effect of load capacitance on the delay also shows that the CMOS is better and PAL gives less delay than CAL and IPGL. The area consumed by each logic circuit is shown in figure 6. a. Energy Dissipated verus VDD 0 2 4 6 8 10 12 14 16 18 20 1.201.501.802.10 VDD (V) Energy Dissipated (pJ) CMOS CAL PAL IPGL b.Energy Dissipated versus Frequency of Select 0 5000 10000 15000 20000 25000 6.25 7.81 10.42 15.63 31.25 69.44 89.29 125.00 208.33 625.00 Select Frequency (MHz) Energy Dissipated (pJ) CMOS CAL PAL IPGL c.Energy Dissipated versus CL 0 1 2 3 4 5 6 7 8 2.885.768.6411.5221.6043.2064.8086.40 Load Capacitance (fF) Energy Dissipated (pJ) CMOS CAL PAL IPGL Figure 4. Energy dissipated 406 a. Delay versus Select Frequency 0 5 10 15 20 25 6.25 6.94 7.81 8.93 10.42 12.50 15.63 20.83 31.25 62.50 69.44 78.13 89.29 104.17 125.00 156.25 208.33 312.50 625.00 Select Frequency(MHz) Delay (ns) CMOS CAL PAL IPGL b.Delay versus CL 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 2.885.768.6411.5221.6043.2064.8086.40 Load Capacitance (fF) Delay(ns) CMOS CAL PAL IPGL Figure 5. Delay Measurements Area 0 5 10 15 20 25 30 CMOSCALPALIPGL Logic Style No of MOSFETS No of PMOS No of NMOS Total no of MOSFETs Figure 6. Area in terms of Transistors 5. Conclusion With the energy-recovery adiabatic switching, the circuit energies are conserved within the system rather than dissipated as heat. Depending upon the system requirements and application, this approach may be used to design ultra low power under certain conditions. These conditions are obviously defined by frequency constraints, device sizes, and silicon area overhead. Barrel shifter design can be optimized for low power, low delay and area using the results published here. Simulation time can be considerably reduced now as the specific logic style can be selected for the given frequency of data and used repetitively. The number of MUX used in a barrel shifter is nlog2n and all the three parameters viz. area, power and delay can be scaled by the same amount. The parasitic effect can be also measured for individual MUX and scaled and subtracted. Thus, if adiabatic multiplexers are used in designing barrel shifter, the energy dissipation also can be minimized. PAL logic offers the best solution as its energy delay product is the lowest at Vdd=1.2V, select signal frequency higher than 50 MHz and load capacitance greater than 11.52 fF. It can be also proved that overall energy dissipation and delays will be nlog2n times the value shown in the above results. 6. References 1Jan Rabey, Massoud Pedram. Low Power Design Methodologies: 5-7. Kluwer Academic Publishers, 5th edition 2002. 2Michael Frank. Energy-Power Basics. Lecture notes, University of Florida. 3 P D Khandekar, S Subbaraman, Manish Patil, “Optimising 2:1 MUX for Low Power Using Adiabatic Logic” International Conference on VLSI Design ICVLSI08,VEC, Chennai, 14-16 Feb 2008, pp 145-150. 4 William Athas et al, “Low-Power Digital Systems Based on Adiabatic-Switching Principles”, IEEE Transactions on VLSI Systems, Vol 2, no 4, pp398-407, December 1994. 5 Mathew Pillmeier, Michael Schulte