四位全加器的VHDL设计

,四位全加器的VHDL设计,一位全加器真值表,一位全加器的逻辑表达式,S=ABCinCo=AB+BCin+ACin其中A,B为要相加的数，Cin为进位输入；S为和，Co是进位输出；,Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntityfulladderIsPort(Ci,a,b:INstd_logic;s,Co:OUTstd_logic);Endfulladder;Architecturem1OffulladderIsSignaltmp:std_logic_vector(1downto0);Begintmp=(0,一位全加器的数据流（逻辑）描述,Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntityfulladderisPort(A,B,CI:instd_logic;S,CO:outstd_logic);Endfulladder;ArchitecturedataflowoffulladderisBeginS=CIxorAxorB;CO=(AandB)or(CIandA)or(CIandB);Enddataflow;,一位全加器的行为描述,Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntityfulladderisPort(a,b,cin:Inbit;sum,cout:Outbit);Endfulladder;ArchitecturebehaveOffulladderIsBeginProcess(a,b,cin)BeginIf(aOrbOrcin)=0Thensum=0;cout=0;Elsif(aANDbANDcin)=1Thensum=1;cout=1;Elsif(aXORbXORcin)=0Thensum=0;cout=1;Elsesumy(0),s=sum(0),Co=c(1);U2:fulladderPortMap(c(1),x(1),y(1),sum(1),c(2);U3:fulladderPortMap(c(2),x(2),y(2),sum(2),c(3);U4:fulladderPortMap(c(3),x(3),y(3),sum(3),c(4);Cout=c(4);Endax;,libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityadder4bitisport(cin:instd_logic;a,b:instd_logic_vector(3downto0);s:outstd_logic_vector(3downto0);cout:outstd_logic);endadder4bit;architecturebehofadder4bitissignalsint:std_log