用VHDL语言设计555压控振荡器测频率

实验五 利用压控振荡器测量电压一、实验目的（1）以555定时器为基础设计压控振荡器（2）设计一个具有如下功能的简易频率计。 1. 可以测量压控振荡器产生的频率，用4位数码管显示 2.测量结果直接用十进制数值显示 3. 被测信号是压控振荡器产生的方波脉冲信号，根据设计的压控振荡器确定电压值 4. 具有超量程警告（可以用 LED 灯显示）二、实验设备与器材（1）计算机：Quartus 16.0软件；（2）硬件：Cyclone DE0-CV FPGA开发平台、555定时器、电阻、电容、可变电阻三、利用Multisim搭建仿真电路四、实验程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;- 计数器entity cnt10 is port (rst,fx,ena:in std_logic; cout: out std_logic; outy :out std_logic_vector(3 downto 0);end cnt10;architecture behv of cnt10 isbegin process (rst,ena,fx) - 定义变量 - 0是对数组cqi所有元素赋值0 if rst=1 then cqi :=(others =0); elsif fxevent and fx=1 then if ena =1 then if cqi 9 then cqi:=cqi+1;cout0); cout0); end if; end if; outy fx,rst=rst,ena=ena,cout=e(0),outy=d(3 downto 0);u2:cnt10 port map(fx=e(0),rst=rst,ena=ena,cout=e(1),outy=d(7 downto 4);u3:cnt10 port map(fx=e(1),rst=rst,ena=ena,cout=e(2),outy=d(11 downto 8);u4:cnt10 port map(fx=e(2),rst=rst,ena=ena,cout=e(3),outy=d(15 downto 12);u5:led_hehe port map(ena=e(3),clk=clk,q=led_a);end architecture one;- 16位锁存器 latch=闩library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity latch4 isport(d:in std_logic_vector(15 downto 0);ena,clk:in std_logic;q:out std_logic_vector(15 downto 0);end latch4;architecture one of latch4 isbegin process(clk,ena,d) variable cqi:std_logic_vector(15 downto 0); begin if ena=0 then cqi:=cqi;- ena=0 锁存上次的数据 elsif clkevent and clk=1 then cqi:=d;-clk=1&ena=1 计入新数据 end if; q=cqi; end process; end one;- 报警led hehelibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity led_hehe isport(ena,clk:in std_logic;q:out std_logic);end led_hehe;architecture one of led_hehe isbegin process(clk,ena) variable cqi:std_logic; begin if ena=0 then cqi:=cqi;- ena=0 锁存上次的数据 elsif clkevent and clk=1 then cqi:= not cqi;-clk=1&ena=1 计入新数据 end if; q a a a a a a a a a a a a a a a a null; end case; end process;end;- 控制模块(每隔一次clk，就翻转ena和rst)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity control is port (clk:in std_logic; rst,ena: out std_logic);end control;architecture behv of control isbegin process (clk) variable cqi :std_logic_vector(2 downto 0); begin if clkevent and clk=1 then if cqi 1 then cqi:=cqi+1;ena=1;rst0); ena=0;rst=1; end if; end if; end process;end behv;- 时钟（1hz）发生器library ieee;use ieee.std_logic_1164.all;entity freq_div is port (clk:in std_logic; clk_out:out std_logic); end freq_div;architecture fwm of freq_div isconstant m: integer:= 25000;signal tmp:std_logic;begin process(clk,tmp) variable cout:integer:=0; begin if clkevent and clk=1 then cout:=cout+1; if cout=m then tmp=0; elsif coutm*2 then tmp=1; else cout:=0; end if; end if; end process;clk_outclk,clk_out=clk_base);u2: control port map(clk=clk_base,ena=x,rst=z);u3: cnt10_4 port map(fx=fx,rst=z,ena=x,d=g,led_a=leds(28),clk=clk_base);u4: latch4 port map(clk=clk_base,ena=x,d=g,q=h);u5: led_controller port map(d(3 downto 0)=h(3 downto 0),a(6 downto 0)=leds(6 downto 0);u6: led_controller port map(d(3 downto 0)=h(7 downto 4),a(6 downto 0)=leds(13 downto 7);u7: led_controller port map(d(3 downto 0)=h(11 downto 8),a(6 downto 0)=leds(20 downto 14);u8: led_controller port map(d(3 downto 0)=h(15 downto 12),a(6 downto 0)=leds(27 downto 21);ledout=leds;end;-引脚配置说明：- port(clk:in std_logic;- fx:in std_logic;- ledout:out std_logic_vector(27 downto 0);