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A STUDY OF DIGITAL DECODERS IN FLASH ANALOG-TO-DIGITAL CONVERTERS Erik Sll, Mark Vesterbacka and K. Ola Andersson Dept. of E.E., Linkping University, SE-581 83 Linkping, Sweden eriks, markv, olaaisy.liu.se ABSTRACT Digital decoders in fl ash analog-to-digital converters are studied. An attractive approach for realizing the decoder is to count the ones in the thermometer coded comparator outputs with, e.g., a Wallace tree. Such a ones-counter can be fast and it incorporate global bubble error correction. We also suggest an improvement of the Wallace tree decoder, obtained by applying folding. This yields a decoder with less area and a circuit with shorter critical path, which should make it possible to design for lower power consumption than the Wallace tree decoder. The folded decoder also enables introduction of extra bubble error correction circuitry for the same hardware cost, or less, as for the Wallace tree decoder, which does not have the extra bubble error correction. This makes the folded decoder not only attractive to high-speed applications, but also to applications where low bit error rate is crucial. 1. INTRODUCTION High speed analog-to-digital converters (ADCs) are usually based on a fl ash structure 123. In these circuits, the input signal is applied to the inputs of 2N1 number of comparators, where N is the number of bits. Each comparator is connected to a reference voltage, commonly generated by a resistive ladder. The outputs of the comparators are connected to latches, that hold the outputs at stable digital zeroes or ones between each sampling instant. The output of a latch is one if the input voltage is larger than the refer- ence voltage at the input of the comparator, otherwise the output is zero. The output pattern of the latches corresponds to thermom- eter code. This code is generally decoded to, e.g., binary code, which is done by the (2N1)-to-N decoder as shown in Fig. 1. Figure 1: Illustration of a fl ash analog-to-digital converter. For low-resolution and low-speed converters, the input to the decoder will indeed be a perfect thermometer code. However, as the resolution is increased the bubble error rate increases, espe- cially if the speed is increased as well. The “bubbles” are zeros introduced in the code, mainly due to two major error sources 1234. The fi rst source is the uncertainty introduced in the effective sampling instant of the comparators. This is due to the global signal propagation over a long distance, which introduces a timing difference between the signal lines and the clock lines. Second, the metastability and error probability of the compara- tors, such as offset, cross talk, limited bandwidth, etc., also give rise to the bubble errors 14. 2. BACKGROUND 2.1 ROM Decoder A common approach to decode the thermometer code is to use a gray or binary-encoded ROM. The appropriate row m in the ROM is selected by using a circuit that has the output of comparator m and the inverse of comparator m+1 as inputs. The output is one if the output of comparator m is one and the output of comparator m+1 is zero. This may be realized by, e.g., a 2-input AND gate, where one input is inverted. However, this solution selects multi- ple rows if bubble errors occur, which introduces large errors in the output of the decoder 12. If only single bubble errors occur, this can be corrected for by using 3-input NAND gates, as illustrated in Fig. 2. This solution removes all bubble errors if they are separated by at least three bits in the thermometer scale. Figure 2: Illustration of a fl ash ADC with ROM decoder 2. + + + R R R R VIN (2N-1)-to-N decoder Vref,p Vref,n N-bit + R VIN Vref+ + + R R R Vref- + + R R CK OUT ? The main advantage of this ROM decoder approach is that it is simple and straightforward to design. It is, however, a slow and power consuming solution. Another disadvantage is that as the speed increases, more bubble errors are introduced and a more advanced bubble error correction scheme than the 3-input NAND is required. This further reduces the speed of the decoder as well as adds to the overall power consumption. 2.2 Using a ones-counter as decoder The output of a thermometer-to-binary decoder is the number of ones on the input, represented in, e.g., gray or binary code. This is utilized when using a ones-counter as a decoder and gives the same result as the bit swapping technique 5. However, the bit swapping technique also requires a thermometer decoder, since the output is a bubble error corrected thermometer code 5. Using the ones-counter the output is the decoded binary code and it also applies global bubble error correction/suppression 1. Another benefi t of the approach of using the ones-counter as a decoder is that, depending on the speed requirement on the ADC, a suitable ones-counter topology may be selected by trading speed for power. In our case, we are looking for a decoder to be used in high-speed applications. This implies that a high-speed ones- counter is suitable, which makes the Wallace tree topology (Fig. 3) a good choice 16. Figure 3: Wallace tree decoder for a 4-bit fl ash ADC 1. 3. COMPARISON OF THE APPROACHES Using a ones-counter as the decoder allows speed/power trade-off not only by directly trading power for speed, but also in terms of choosing an appropriate ones-counter/adder topology. Hence, this approach is more attractive than other solutions, such as the ROM decoder. In the ROM decoder the power consumption is, to a large extent, set by the manufacturing process used, and the ROM decoder may limit the speed in high-speed applications 1. Mat- lab models have been developed to further investigate the differ- ent approaches. The timing difference between the signal lines and the clock lines (t) is assumed to have a Gaussian distribution .(1) Assuming the input to be a sinusoid, with the peak-to-peak magnitude equal to the full scale voltage (VFS=Vref) and with the frequency fIN, the effect of the timing difference can be modelled by a normally distributed offset voltage on the input of the com- parators (Fig. 4), according to .(2) Figure 4:Comparator model. As seen in Fig. 4 this model can also be used to include the inherent offset of the comparators due to mismatch. The results of the simulations are shown in Fig. 5(a)-(c). (a) N=6. (b) N=8. (c) N=10. Figure 5:Effective number of bits (ENOB) for different decoders as a function of standard deviation of the timing differences between the clock lines and signal lines. FA FA FA FA FA FA FA FA FA FA FA C1 C2 Ci C15 C3 C13 LSB MSB tN 0 t,() VN 0 tfINVFS,() + VIN Vref,j V 00.0020.0040.0060.0080.01 4.8 5 5.2 5.4 5.6 5.8 6 6.2 t ENOB 1s counter or Bit swapping 3?input NAND 00.0020.0040.0060.0080.01 5 5.5 6 6.5 7 7.5 8 8.5 t ENOB 1s counter or Bit swapping 3?input NAND 00.0020.0040.0060.0080.01 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 t ENOB 1s counter or Bit swapping 3?input NAND ? The “3-input NAND” curves in Fig. 5(a)-(c) correspond to the bubble error correction logic in the ROM decoder, where 3-input NAND gates are used to suppress bubble errors (Fig. 2). The out- put of gate m generates the corrected thermometer code for level m and gate m has the levels m, m+1 and m+2 as inputs. From Fig. 5 it is seen that the effective number of bits are equal or higher for the ones-counter decoder, compared with the other solutions. Hence, the approach of using a ones-counter yields higher performance of the ADC. This is why we focus on the ones-counter decoder and, especially, the Wallace tree decoder and investigates what improvements of this solution that are pos- sible. 4. SUGGESTED IMPROVEMENTS In a folded fl ash ADC, the idea is to reduce the amount of hard- ware by using the same comparator for different reference volt- ages 7. This is the idea our folded Wallace tree decoder, shown in Fig. 6, is based on. Figure 6:Illustration of the folded Wallace tree decoder. The size of the Wallace tree and the delay is depending on the number of bits that are to be added, i.e., the width of the base of the tree. The idea is to split the output of the comparators into 2k different intervals, which are multiplexed to a single Wallace tree decoder, which is reduced in size compared with the one in 1. According to 1 the number of adder cells needed (xN) and the critical path (cN) is (3) and ,(4) respectively, where each cNis equal to tXOR(tXOR=propagation delay of an XOR gate), since this is the propagation delay of a full adder (FA) 89. In our case, since the output range is split into 2klevels, the number of adder cells required, and the critical path in terms of tXOR, becomes (5) and .(6) Multiplexers are required before the adder tree, and the number of multiplexers is 2Nk, where each multiplexer is of the type 2k- to-1. A full adder may be built up of three 2:1 multiplexers and if it is assumed that, e.g., a 4:1 multiplexer consists of three 2:1 mul- tiplexers (according to Fig. 7), a 4:1 multiplexer is similar to a full adder in terms of required hardware and thereby have a similar area and power consumption cost. Figure 7:Illustration of 4-to-1 (4:1) multiplexer. This solution, shown in Fig. 7, is however not optimal. Our results are thereby somewhat pessimistic, although they clearly show the benefi ts of using our folded decoder. The new expres- sion for the number of full adders is .(7) The critical path in units of tXORmay be calculated according to , where the propagation delay of a full adder is assumed to be 2tXOR89, and 1tXORfor a 2-to-1 multiplexer. A comparison of the performance between the Wallace tree decoder (k=0) and the folded decoder, in terms of amount of hard- ware and length of the critical path, is given in Table 1. As seen in Table 1, the hardware is signifi cantly reduced when using the folded decoder. For the 4-level folded decoder (k=2), the number of full adders are reduced by more than 50% compared to the Wallace tree decoder in 1. This is likely to translate to a power saving. 2N-1 0 2N-k 2N-k 2N-k Wallace tree decoder 2N-k 2N-k N-k LSB MSB-k MSB-k+1 MSB MUX Control k P1P2k-1 IN 2N-k 2N-k 2*2N-k 3*2N-k P0 P0 P1 P2 xNi1() 2 Ni() i1= N = cN4 N6 N1,= Type of decoderN.o. FAsCritical path Wallace tree decoder (k=0)247 FA26 tXOR 2-level Folded decoder (k=1)163 FA23 tXOR 4-level Folded decoder (k=2)121 FA20 tXOR Table 1: Performance comparison for an 8-bit fl ash ADC. xNi1() 2 Nki() i1= Nk = cN4Nk()6 Nk1,= C1 2 3 C0 0 1 C0 0 1 C0 0 1 C1 0 1 xNi1() 2 Nki() i1= Nk =2N k 2k1 3 - -+ Tc N tXOR4N3k6(), Nk1= ? Table 1 also indicates that the folded decoder has a reduced crit- ical path, which indicates that the suggested solution has the potential of being faster than the Wallace tree decoder. The fact that our solution has a shorter critical path also makes it possible for some trade-offs in the decoder. The speed of each device may be reduced, which would further reduce the power consumption. It should, however, be noted that the propagation delay of the multiplexer control circuitry is not included in the critical path of Table 1. This does not affect the result in Table 1 for the 2-level folded decoder, since the signal from the level pointer (Pjin Fig. 6) is connected directly to the multiplexer control signal input. In the 4-level case, the circuitry in Fig. 8 may be used to implement the MUX control circuit, which is a thermometer-to- binary (2 bits) decoder. Figure 8:Multiplexer control circuitry (k=2). If the propagation delay of each gate is assumed to be equal to tXOR, as a worst case, the critical path of the 4-level folded decoder is the same as for the 2-level folded decoder. However, the amount of hardware is less. If the decoder is folded further, the multiplexer control circuitry of an 8-level (or higher) folded decoder adds too much to the critical path, which results in an even slower circuit, compared to the Wallace tree decoder in 1. This is why we only consider the 2 and 4-level folded decoder in Table 1. If error correction circuitry is used, the OR gates (see Fig. 6) that are detecting which level that is active, are unnecessary. How- ever, if bubble error correction is not used, the OR gates have to be included. The size of the gate (number of inputs) depends on how many bubble errors that may be present. More bubble errors makes it necessary to have a larger OR gate to ensure that the cor- rect level is active (three inputs are used in Fig. 6). The Wallace tree decoder in 1 corrects for global bubble errors, but if more than one bubble error occurs during the same sample, an offset error shows up in the output. If the bit error rate is an important issue for the application, some extra bubble error correction circuitry must be added before the decoder, to the cost of extra hardware, longer critical path and higher power consump- tion. The amount of hardware is reduced using our folded decoder and the bubble error correction circuitry only has to be applied to 2Nklevels (the output of the multiplexer). Hence, the hardware cost, critical path and power consumption may be lower using the folded decoder with extra bubble correction circuitry, compared to the Wallace tree decoder without the extra bubble error correc- tion. This makes the folded decoder not only attractive to high- speed applications, but also to applications where low bit error rate is an important issue. 5. CONCLUSIONS Our study shows that the ones-counter decoder is an attractive approach for designing thermometer-to-binary code decoders. This type of decoders is fast if the Wallace tree topology is used, and they incorporate global bubble error correction. The sug- gested improvement of the Wallace tree decoder, by applying folding, result in a decoder with less area and a circuit with shorter critical path. This should make it possible to design for lower power consumption than the Wallace tree decoder. The folded decoder also enables to the introduction of extra bubble error correction circuitry for the same hardware cost, or les