基于FPGA的串口控制器设计外文文献翻译、中英文翻译

The serial controller design based on FPGAIntroductionThe use of hardware description language (HDL) is becoming a more dominant factor, when designing and verifying FPGA designs. The use of behavior level description not only increases the design productivity, but also provides unique advantages in the design verification. The most dominant HDL stoday are called Verilog and VHDL. This application note will illustrate the use of Verilog in design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).Defining the UART.The UART consists of two independent HDL modules. One module implements the transmitter, while the other module implements the receiver. The transmitter and receivermodules can be combined at the top level of the design, for any combinations of transmitter and receiver channels required. Data can be written to the transmitter and read out from the receiver, all through a single 8 bit bi-directional CPU interface. Address mapping for the transmitter and receiver channels can easily be build into the interface at the top level of the design. Both modules share a common master clock called mclkx16. Within each module mclkx16 are divided down to independent baud rate clocks.UART functional overview.A basic overview of the UART is shown below. At the left hand side is shown “transmit hold register”, “transmit shift register” and the transmitter “control logic” block, all contained within the transmitter module called “txmit”. At the right hand side is shown the “receive shift register”, “receive hold register” and the receiver “control logic” block, all contained within the receiver module called “rxcver”. The two modules have separate inputs and outputs for most of their control lines, only the bi-directional data bus, master clock and reset lines are shared by both modules.UART timing diagrams.Below is shown, how data written to the “transmit hold register” gets loaded into the “transmit shift register”, and at the rising edge of the baud rate clock, shifted to tx output.The Transmitter module.The master clock called mclkx16 are divided down to the proper baud rate called txclk and equals to mclkx16/16. Data written in parallel format to the module are latched internally, and shifted in serial format to the tx output at the frequency of the baud rate clock. Data shifted to the tx output follows the UART data format shown in fig. 6.Behavioral description of the transmitter.The transmitter waits for new data to be written to the module. When new data are written a transmit sequence is initialized. Data that was written in parallel to the module gets transmitted as serial data frames at the tx output. When no transmit sequence are in place, the tx output is held high.Implementation of the transmitter module. Internal signals in Verilog are declared as “wire” or “reg” data types. Signals of the “wire” type are used for continuos assignments, also called combinatorial statements. Signals of the “reg” type are used for assignments within the Verilog “always” block, often use for sequential logic assignments, but not necessarily. For further explanation see a Verilog reference book. Data types of the internal signals of the module can be referred to in table 3.We have now passed by all necessary declarations, and are now ready to look at the actual implementation. Using hardware description language allows us to describe the function of the transmitter in a more behavioral manner, rather than focus on its actual implementation at gate level. In software programming language, functions and procedures breaks larger programs into more readable, manageable and certainly maintainable pieces.A Verilog function and task are used as the equivalent to multiple lines of Verilog code, where certain inputs or signals affects certain outputs or variables. The use of functions and tasks usually takes place where multiple lines of code are repeat edly used in a design, and hence makes the design easier to read and certainly maintain.A Verilog function can have multiple inputs, but always have only one output, while the Verilog task can have both multiple inputs, and multiple outputs. Below is shown the Verilog task, that hold all necessary sequential statements, to describe the transmitter in the “shift” mode.We here see the two tag bits called tag1 and tag2 concatenated to the “transmit shift register.Similar tasks were created to describe the transmitter in “idle” and “load”modes.By using these Verilog tasks, we can now create a very“ easy to read” behavioral model of the hole transmit process.If tx done and tx datardy both are true, the transmitter enter load mode. Next to the lo ad mode, the transmitter enters shift mode. At the rising edge of the baud rate clock, the contents of tsr are shifted to the tx output. Parity generation takes place during shifting of the tsr, as shown below.Simulation of a transmit sequenceThe contents of the data bus are latched into thr at the rising edge of write. At the next rising edge of txclk, the contents of thr are loaded into tsr, the active low start bit is a asserted to tx, and the txrdy flag indicates, that thr again is ready for new data to be written. At each rising edge of txclk, the contents of tsr is shifted to tx. Parity generati on takes place during shifting of data. Parity cycle is high one cycle next to last cycle, and tx gets the parity result.The Receiver module.The master clock mclkx16 are divided down to the proper baud rate clock called rxclk, and equals to mclkx16/16. Serial data to be received at the rx input of the module,mu st follow the UART data format. Data received in serial format can be read out in parallel format, through the 8 bit data bus.Behavioral description of the receiver.Between successive transmissions, the transmission line is held high, according to standard UART behavior. The receiver waits in “idle” mode for the rx input to go low. At the falling edge of rx the receiver enter “hunting” mode, now searching for a valid start bit of a new data frame to be received. If a valid start bit is detected, the receiver enter “shift data” mode. During receive of a data frame, various parity and error checks are performed. When a complete data frame has been received the receiver returns to idle mode. The basic operation of the receiver works as shown below.Implementation of the receiver module.In order to create an easy to read and easy to maintain behavioral model of the recei ver two Verilog tasks are written to describe the different modes of the receiver. The Verilog task called “idle_reset” holds all necessary sequential statements to describe the receiver at reset condition, and when the receiver is in its idle mode.When the receiver is not at its reset condition, and not in its idle mode, the receiver samples data at the rx input, shifts the data to the “receive shift register”, and genera tes parity based on the incoming data. The Verilog task called “shift_data” holds all necessary sequential statements to describe all above actions. Using the two Verilog tasks described above, we are now able to create the behavioral level description of the receiver at its reset condition, idle mode or when shifting in date . All above actions is synchronous to the baudrate clock called rxclk, and the im plementation is shown below.A complete data frame has been received, when the leading low start bit reaches rsr0, and the receiver returns to idle mode again at the next rising edge of rxclk. At return to “idle” mode the receiver raises the “receive data ready” interrupt to indicate, that the new data received now can be read out in parallel format. Error flags are updated as well upon return to “idle” mode, and cleared when data are read out of the receiver. At the falling edge of read, the contents of the rhr are latched to the data bus. In table 8 shown below are the various error checks supported by the receiver.Simulation of a receive sequence.Between successive transmissions, the transmission line is held high. At the falling edge of rx input, the internal rxcnt starts counting up, synchronous to mclkx16. If rx input stays low for 8 cycles of mclkx16, the internal status bit idle is reset, and there by enable generation of rxclk. Rxclk is now synchronized to the center point of the l ow start bit. At the rising edge of rxclk, data are shifted from the rx input to rsr. When the leading low start bit reach rsr0, the next rising edge of rxclk forces idle high aga in and there by disable generation of rxclk.At return to idle mode, the contents of rsr are loaded into rhr, the status flags are updated. The flag “rxrdy” now indicates, that the contents of rhr can be read out. At the falling edge of read, the contents of rhr are applied to the data bus.Using Hardware Description Language for Simulation.We have now studied how HDL can be used for the behavioral level design impleme ntation of a digital UART. While HDL make the design implementation easier to read and hopefully to understand as well, it also provides the ability to easily describe dep endency in between various processes that usually occur in such a complex event dri ven systems, as for example the UART. This ability to describe dependency in betwe en various processes is extremely need for simulation purposes as we will see very so on.Simulation stimulus in Verilog HDL is called a “test fixture”. A test-fixture is a V erilog module that holds all lines of HDL code necessary to generate the simulation stimulus, while it at the same time port maps these signals to the design that are to be simulated. The port mapping is done by hierarchical module instantiation of the UAR T top level module into the test-fixture, as shown below.This allows simulation stimulus to be applied to the inputs of the design, while monit oring the outputs of the design. Input stimulus can be made conditionally to the response on the outputs ect. In fig. 19 shown below is illustrated, how the test-fixture port maps to the top level of the UART.Within the test-fixture the tx output of the transmitter module is looped back to the rx input of the receiver module. This allows the transmitter module to be used as test sig nal generator for the receiver module. Data can be written in parallel format to the tra nsmitter module and looped back in serial format to the rx input of the receiver modu al and data received can finally be read out in parallel format from the receiver modu al. In order to automate the testing of the UART as much as possible, tree independent Verilog tasks were written as follows. The Verilog task“write_to_transmitter” holds all necessary statements required to generate a single parallel data write sequence to the transmitter module. Data that are written to the transmitter upon execution of the “write_to_transmitter” task, get latched internal to the test-fixture for later analysis. The Verilog task “read_out_receiver” holds all necessary statements required to ge nerate a single parallel data read out sequence from the receiver module. Data that are read out of the receiver upon execution of the “read_out_receiver” task, get latched internal to the test-fixture for later analysis. The Verilog task “compare_data” holds all necessary statements required to compare the previous data written to the transmit ter module, to the corresponding and most recent data received and read out from the receiver module. If any discrepancy occurs, the “compare_data” task flags for an err or by writing out the data values that were written to the transmitter module, as well as the corresponding data values that were received by and read out from the receiver module. Silicon for synthesis.While HDL as design implementation method offers several advantages over traditio nal FPGA design entry approaches such as schematic capture, it meanwhile require great flexibility as well as high performance by the target devices for the synthesis flow. The synthesis flow for the UART has been targeted two flexible and high perfo rmance FPGA architectures available from QuickLogic, called the pASIC-1 and the pASIC-2 families.After synthesis, the design were placed & routed using the Place & Route tools from QuickLogic. After the Place & Route, the UART design were simulated using back-annotated Verilog post-layout timing models. The fast Verilog simulator called Silos III from Simucad were used for the post-layout simulation. All used tools are available within the QuickWorks tool suite from QuickLogic. 基于FPGA的串口控制器设计简介使用硬件描述语言 (HDL) 设计和开发验证FPGA成为当前的主流因素。使用行为级描述不仅增加了产品的设计效率，也在设计中有独特的验证方式。目前最流行的HDL语言为Verilog 和 VHDL。这篇文章将会举例说明用 Verilog语言设计和验证数字异步串行收发器UART。UART介绍 通用异步串行收发器UART包含两个独立的VHDL模块。一个模块实现发射功能, 另一个实现接收功能，发射和接收功能模块在顶端设计时组合到一起使用,接收和发射的组合是通信通道所必需的。数据写入发射器，从接收器读出，所有的数据以二进制8字节的信号通过CPU接口。地址映射的发射机和接收机通道可以很容易的在设计顶层的接口构建。两者共用一个称为mclkx 16的主控时钟，在每个模块中 mclkx 16 被分成独立的波特率时钟。UART的功能概况UART的基本功能概况见下表。在左边显示传输保持记录，移位记录，传输控制时钟，全部集中在发射机的txmit端。在右边显示接收移位寄存器，接收记录和控制逻辑时钟，所有都包含在接收模块的rxcver端，这两个模块有单独的输入和输出的控制线路，只有双向的数据总线，主时钟和复位线由两个模块共享。顶层UART系统的I/O功能描述UART时序图下面显示的是写入传输寄存器的数据是如何被加载到移位寄存器，并在波特率时钟的上升沿，转向txd输出端。发送器主控时钟mclkx16被分频到合适的波特率时钟称为rxclk，它等于mclkx16/16。数据以平行的形式锁存模块，而转向以串行格式在波特率时钟频率下向tx端输出。数据转到tx输出遵循UART数据格式如图6所示。发送器行为描述发送器等待新的数据写入模块，当新的数据写入发送序列模块时数据初始化。被写入的数据以并行方式传送到发送模块然后被转化成串行数据帧从tx输出。当没有传输序列的地方，tx输出是高电平。发送器实现 Verilog的内部信号被称为wire和reg两种数据类型，WIRE类型的信号用于连续的作业，也称为组合语句，REG类型的信号用在分配Verilog里的always时钟,常常使用逻辑顺序的分配,但不是一定的，进一步解释见Verilog参考书，模块内部信号的数据类型如表3所示。我们现在已经通过了所有必要的声明，并已作好准备，看看实际执行，用硬件描述语言使我们以更加行为化的方式描述发送器的功能，而不是把重点放在它在门级的实际执行情况。在软件编程语言中，函数和程序将大项目分解成更具可读性，管理性，当然也可维护的部件，Verilog的函数和任务被用来当作多行的Verilog代码,其中某些输入或信号影响某些输出或变量。函数和任务的使用,通常发生在多行代码需要重复使用的设计中，从而使得设计易于阅读和维护肯定，Verilog函数,可以有多种输入，但始终只有一个输出，然而Verilog任务可以兼得多投入，多产出，下面显示了Verilog任务，即拥有所有必要的顺序语句，用来描述发送器的转移模式。我们可以看到在移位寄存器里有2个标志位叫作tag1和tag2，在描述空闲和置位模块时产生相同的作用。使用这些 Verilog 工作，我们现在可以产生一个非常容易阅读的行为模型的空穴传输过程。如果txdone 和txdatardy都是正确的，发送器进入负载模式。在负载模式下，进入发送模式转变，在上升沿的波特率时钟，tsr的内容转移到tx输出端。 奇偶校验过程产生于tsr变化中，如下所示。模拟发送序列在写入上升沿时数据总线容量被锁存，在txclk下一个上升沿，thr的容量载入tsr，低电平开始位进入tx，发送标志位显示，thr再次等待新的数据的写入。在每个发送时钟上升沿，tsr的容量被送入tx，在数据传输过程中产生奇偶校验，周期循环时奇偶校验为高电平，tx产生奇偶校验结果。接收模块主控时钟mclkx16被分频到合适的波率时钟称为rxclk，它等于mclkx16/16 。 串行数据为收到的rx输入模块，必须按照UART的数据格式，串行格式接收到的数据通过8位数据总线以并行格式的形式读出。接收模块行为描述根据标准异步串行UART行为标准，在连续发送时，发送保持高电平，接收器在等待闲置模式的rx端输入为低电平，在rx下降沿接收进入保持模式，现在寻求一种有效的开始位等待新的数据帧的到来，如果一个有效的开始位被检测到时，接收器进入转变数据模式，在接收一个数据帧的过程中,各种校验和检查错误被执行，当一个完整的数据帧被接收，接收端返回待机模式，接收器基本运作如下所示。接收器模块的实现为了产生一个易读易操作的接收器模块，用两种Verilog任务来描述不同的接收方式，当接收在空闲状态时，其中一个Verilog任务称为空闲复位，而它需要所有必要的顺