AD574中英文翻译解析

12位-AD574A转换器【摘要】AD574是美国Analog Device公司生产的12位单片A/D转换器。它采用逐次逼近型的A/D转换器，最大转换时间为25us，转换精度为0.05%，所以适合于高精度的快速转换采样系统。芯片内部包含微处理器借口逻辑（有三态输出缓冲器），故可直接与各种类型的8位或者16位的微处理器连接，而无需附加逻辑接口电路，切能与CMOS及TTL电路兼容，在多种复杂环境下能正常工作。关键词： 高精度 逐次逼近型 转换器 电路工作原理AD574A是一个完善的12位A/D转换器，不需要外部组件提供完全的逐步逼近模拟数字转换功能。图1所示为AD574A的方块结构图。图1 AD574A的方块结构图当控制部分收到初始化转换命令（后边会叙述）时，会开启时钟并把连续逼近寄存器（SAR）全部置零。一旦转换周期开始，它就不能终止或重新开始，也不能从输出缓冲中读数。时钟控制SAR寄存器的时序，SAR会安排好转换周期的顺序并向控制部分返回一个“转换结束”（end-of-convert）标志。接着，控制部分停止时钟，把输出状态标志位置低，并允许控制函数，以便外部命令可以执行数据读取功能。 在转换周期期间, 内部12 位当前的产品DAC 由SAR 程序化从最高位(MSB) 对最低有效位(LSB)通过5 k(或10k) 输入电阻器提供准确地平衡输入信号。比较器确定位电流的连续增大是否造成了DAC当前总电流比输入电流增大或者减小; 如果总电流较小，此位被留下; 如果总电流较大，位被关闭。 在测试完所有位以后， SAR包含了准确表示输入信号在+1/2 LSB之内的12位二进制编码。 温度补偿是外部提供给DAC基准电压并保证准确的转换的时间和温度的稳定性。基准在10.00 0.2%伏之间平衡，当AD574A使用15伏电源时，除了按要求向参考输入电阻提供0.5mA，向双极偏移电阻提供1mA电流外，它可以给外部负载提供提供高至1.5mA的电流。如果AD574A使用12伏电源，或者外部电流必须在全部温度范围内提供，那么我们推荐使用一个外部的缓冲放大器。任何在AD574A参考手册上的外部负载都必须在转换过程中保持稳定。要调整薄膜应用电容以匹配DAC（数模转换器）的实比例输出电流。有两个5千欧的输入测量电阻允许10伏或20伏的区间。10千欧的双极偏移电容接地用于单极操作，或连接到10伏参考电压上用于双极性操作。AD574模拟输入电压图2 OP放大器与AD574连接OP放大器的输出阻抗有一个开环值，在一个封闭回路中，这个值被回路增益（由增加的频率产生）等分。放大器应该至少拥有500kHz的回路增益才能和AD574A一起使用。要检查信号源的输出特性是否合适，就要在转换进行中使用示波镜监控AD574的输入端。每12个干扰应该在1秒以内衰减。 关于取样保持器的应用，我们推荐AD585型号。我们推荐让AD711型号和AD544型号取样保持器应在直流电下工作。 虽然AD574A的转换时间最高为35秒，但为了能够实现几个赫兹的频率的精确12位转换还是需要使用采样保持放大器（SHA）的。如果一个驱动AD574A的模拟输入信号电压在转换所需的计时周期中变化超过LSB的一半，那么输入端就需要一个SHA。 AD585是一种高线性的采样保持放大器（SHA），它能够直接驱动AD574A的模拟输入端。AD585的快速采集时间、低孔径和低孔径抖动都很好地使用于高速数据采集系统。考虑到AD574A的转换时间为35秒，并且拥有10Vp-p的输入信号，这是能够实现1.5Hz精确转换时所能用的最高频率。 如图3所示，加上AD585后，最高频率增加到了26kHz。AD585的低输出阻抗、快速连环反应和低损耗能够在变化的周期性负荷工况下维持12位准确性，使它适当用于高精确度转换。 许多其他SHAs达不到12位转换的准确性，并且可能因而减弱系统。 AD585被推荐应用于AD574A的采样与保持。 图3 带采样保持器AD585的AD574AAD574A 电源的滤波、良好地校准和远离高频噪声是异常重要的.。噪声补偿的使用会造成不稳定的输出信号。除非特别要求滤掉输出端的电火花，交换式电源电路建议达到12比特的精确度。注意： 一点点毫伏的噪声就代表着12比特ADC（电源）的巨大误差。 电路布局应该尝试定位AD574A,与之相连的相似物输入电路,并使其从逻辑电路上尽可能连接起来.因为这个原因,不推荐使用线路电路结构.应该选择好的印刷的电路体系.逻辑控制AD574A包含了芯片上逻辑，可以通过微处理器中通常存在的信号中提供开始转换和读取转换结果操作” 如图6是AD574A的内部逻辑电路。控制信号CE 、CS, 和R/C 控制交换器的操作。R/C 的状态由CE 和CS 两个信号的加入来确定进行数据读取(R/C = 1) 或数据转换(R/C = 0) 。记数器控制输入AO ,12/8 控制转换长度和数据格式。AO 线通常被连结到地址总线的最低有效位。如果AO置低(电位)开始, 按12 位A/D进行转换。当12/8=1时，12位数据线一次读出，主要用于16位微机系统；12/8=0时，可与8位机接口。此引脚输入为高电平时，12位数据并行输出；当此引脚为低电平时，与引脚A0配合，把12位数据分两次输出。12/8的引脚接DIGITAL COMMON输出8位数据12/8引脚接VLOGIC输出12位数据。12/8的引脚不与TTL兼容的，必须和vlogic或者digital连接，在8位模式下，当Ao置高的时候，低4位加上尾随4个0有效。在不需要内部3态缓冲器的情况下，该结构允许直接接口的8位数据流重叠。在读取转换数据操作时不建议ao改变。三态缓冲器不对称的允许与阻止时间可能造成内部总线冲突,对AD574A造成潜在危害.图4STS这个输出信号表明了转换器的状况。STS值在转换开始时升高，在转换过程完成后降低回原样。AD574A 容易联接于多种微处理器和其他数字化系统。 下列AD574A控制信号的计时要求的讨论应该为系统设计者提供有用的对设备的操作了解。 图5图5显示的是完整的AD574A运作时间矢量图表.坐标轴R/C在CE和CS被捕获之前都应较低;如果R/C显示较高,操作提示会立即发生,并可能引发系统争用.无论CE还是CS都能被用来转换.但是,我们推荐使用CE,因为它比CS有更少的系统延迟,并且能被较快地 输入.在图表7,CE被用来转换. 一旦转换开始STS置成高位，直到转换循环完成,转换开始命令将被忽略。直到转换周期是完全的。在转换期间，输出数据缓冲无效。图8给出了数据读取操作时间状况,在数据读取过程中, 当CE和R/C都处于高电平(假定CS已经处于低电平)的时候,开始测量访问时间. 如果这时CS能够使得设备工作, 访问时间可延长100纳秒.图6在8位的总线接线模式中（和数字公用区连线的12/8 输出）， 地址位AO，必须在CE升高的150毫秒之前和整个读取循环中保持稳定。如果允许AO变化，将会导致对AD574A输出缓存区的损坏。AD5474A单机操作AD5474A可以“独立”模式使用，它是系统里很好用的、可用的和专用的端口，以这种方式不需要用总线连接。按这方式，CE和12/8置成高位，CS和AO置成低位，而转化由RC控制。 当RC置成高位时，三态缓冲器启动，当RC置成低位时开始转换。其允许两种控制信号一种高电位脉冲，低高电位脉冲。由如图11所示的低脉冲操作。在这种情况下R/C下降沿的输出响应被强制为高阻状态，在一个转换周期结束后置回有效逻辑。STS线在R/C变为低电平600ns后变为高电平，当数据有效300ns后恢复低电平。图7如果转换是由如图12所示的高电平脉冲所初始化的，那么在R/C为高电平时，数据链是被允许的。R/C的下降沿启动下一个转换，并且数据链返回到三态（并一直保持三态），知道下一个R/C高电平脉冲出现。图8通常应用R/C单机模式下的低脉冲。图13阐明了典型的8086型处理机的单机构造。额外的74F/S374 插销提高了总线的访问/放行次数并协助简化转炉数-模部分的连接线。图9AD574与单片机接口AD574A的控制逻辑使得绝大多数情况下和微处理器系统总线直接连线变成可能。然而它不可能描述出每一种微处理器类型的接口连接的所有细节，下面将举几个具有代表性的例子。典型的数模转换器接口程序序列涉及以下几步：首先, 在初始化会话的时候，地址被写进数模转换。处理器必须等待会话周期的结束，因为多数数模转换器需要一个以上的指令周期来完成会话操作。当然，有效数据只有在会话结束后才能被读取。AD574A 提供信号端输出(STS) ，它能指示会话过程。这个信号可以由处理器通过读取外部三态缓冲（或其它输入端口）获得。如果系统的计时要求非常严格（请记住AD574A的最大转换时间只有35毫秒）并且处理器在ADC转换周期中有其它任务要做的话，这个STS信号同样可以用于产生一个中断信号传递给转换过程。另一种可行的延时方法是，先假设模数转换器会消耗35微秒来进行转换，然后插入足够多的空指令来保证处理器消耗掉35微秒的时间。一旦建立,即完成转换,可以读取数据.在8位(或数位更少)ADC的情况下,单次读数运行即已足够.在转换器数位多于总线可使用数位的情况下,须选择数据格式,需进行多重读数运行.AD574A含有内部逻辑(器),允许通过选择连接12/8输入而直接到8位或多或16位数据总线界面上。在采用16位数据总线时,(12/8 高)数据总线(DB11 通过 DB0)既可以连接到数据总线的12位有效位或12位无效位。剩余4位应用软件将其掩蔽.到8位数据总线的界面是采用左优格式来实现的。在数位的上半部偶数地址(A0 低)包含 8 MSBs (DB11 通过 DB4).。奇数地址(A0 高)包含 4 LSBs (DB3 through DB0),后面跟有4个零,从而消除数位掩蔽指令.AD574A可以在输入/输出或者储存映像结构中被接线到Z-80 处理机上。图15阐明了一个输入/输出或者映像结构。Z-80使用A0A7 地址线来解码输入/输出端口地址。Z-80的一个有趣的特性就是当进行I/O操作时会自动插入一个等待状态，允许AD574A和时钟频率高达4MHz的Z-80处理器一起使用。对于高于4MHz的实际应用，可以使用图16所展示的等待状态发生器。在配置内存内部，AD574A可以和时钟频率高达2.5MHz的Z-80处理器通过接口相连接。12-Bit A/D Converter【Abstract:】AD574 is a 12 bit A/D converter Analog produced by Device company America. It uses successive approximation type A/D converter, the maximum conversion time is 25us, the conversion precision of 0.05%, fast conversion so suitable for high precision sampling system. The chip contains a microprocessor excuse logic (three state output buffer), so it can be directly connected with the various types of 8 bit or 16 bit microprocessors, without the need for additional logic interface circuit, cutting can be compatible with CMOS and TTL circuit, can work in a variety of complex environment.Keywords high precision successive approximation converterCIRCUIT OPERATIONThe AD574A is a complete 12-bit A/D converter which requires no external components to provide the complete successive approximation analog-to-digital conversion function. A block diagram of the AD574A is shown in Figure 1.Figure 1. Block Diagram of AD574A 12-Bit A-to-D ConverterWhen the control section is commanded to initiate a conversion (as described later), it enables the clock and resets the successiveapproximation register (SAR) to all zeros. Once a conversion cycle has begun, it cannot be stopped or restarted and data is not available from the output buffers. The SAR, timed by the clock, will sequence through the conversion cycle and return an end-of-convert flag to the control section. The control section will then disable the clock, bring the output status flag low, and enable control functions to allow data read functions by external command. During the conversion cycle, the internal 12-bit current output DAC is sequenced by the SAR from the most significant bit (MSB) to least significant bit (LSB) to provide an output current which accurately balances the input signal current through the 5k(or10k) input resistor. The comparator determines whether the addition of each successively-weighted bit current causes the DAC current sum to be greater or less than the input current; if the sum is less, the bit is left on; if more, the bit is turned off. After testing all the bits, the SAR contains a 12-bit binary code which accurately represents the input signal to within 1/2 LSB. The temperature-compensated buried Zener reference provides the primary voltage reference to the DAC and guarantees excellent stability with both time and temperature. The reference is trimmed to 10.00 volts 0.2%; it can supply up to 1.5 mA to an external load in addition to the requirements of the reference input resistor (0.5 mA) and bipolar offset resistor (1 mA) when the AD574A is powered from 15 V supplies. If the AD574A is used with 12 V supplies, or if external current must be supplied over the full temperature range, an external buffer amplifier is recommended. Any external load on the AD574A reference must remain constant during conversion. The thin-film application resistors are trimmed to match the full-scale output current of the DAC. There are two 5 kW input scaling resistors to allow either a 10 volt or 20 volt span. The 10 kW bipolar offset resistor is grounded for unipolar operation and connected to the 10 volt reference for bipolar operation.DRIVING THE AD574 ANALOG INPUTFigure 2. Op Amp AD574A InterfaceThe output impedance of an op amp has an open-loop value which, in a closed loop, is divided by the loop gain available at the frequency of interest. The amplifier should have acceptable loop gain at 500 kHz for use with the AD574A. To check whether the output properties of a signal source are suitable, monitor the AD574s input with an oscilloscope while a conversion is in progress. Each of the 12 disturbances should subside in sorless. For applications involving the use of a sample-and-hold amplifier, the AD585 is recommended. The AD711 or AD544 op amps are recommended for dc applications. SAMPLE-AND-HOLD AMPLIFIERSAlthough the conversion time of the AD574A is a maximum of 35 ms, to achieve accurate 12-bit conversions of frequencies greater than a few Hz requires the use of a sample-and-hold amplifier (SHA). If the voltage of the analog input signal driving the AD574A changes by more than 1/2 LSB over the time interval needed to make a conversion, then the input requires a SHA. The AD585 is a high linearity SHA capable of directly driving the analog input of the AD574A. The AD585s fast acquisition time, low aperture and low aperture jitter are ideally suited for high-speed data acquisition systems. Consider the AD574A converter with a 35 ms conversion time and an input signal of 10 V p-p: the maximum frequency which may be applied to achieve rated accuracy is 1.5 Hz. However, with the addition of an AD585, as shown in Figure 3, the maximum frequency increases to 26 kHz.The AD585s low output impedance, fast-loop response, and low droop maintain 12-bits of accuracy under the changing load conditions that occur during a conversion, making it suitable for use in high accuracy conversion systems. Many other SHAs cannot achieve 12-bits of accuracy and can thus compromise a system. The AD585 is recommended for AD574A applications requiring a sample and hold.Figure 3. AD574A with AD585 Sample and HoldSUPPLY DECOUPLING AND LAYOUTCONSIDERATIONSIt is critically important that the AD574A power supplies be filtered, well regulated, and free from high frequency noise. Use of noisy supplies will cause unstable output codes. Switching power supplies are not recommended for circuits attempting to achieve 12-bit accuracy unless great care is used in filtering any switching spikes present in the output. Remember that a few millivolts of noise represents several counts of error in a 12-bit ADC.Circuit layout should attempt to locate the AD574A, associated analog input circuitry, and interconnections as far as possible from logic circuitry. For this reason, the use of wire-wrap circuit construction is not recommended. Careful printed circuit construction is preferred.CONTROL LOGICThe AD574A contains on-chip logic to provide conversion initiation and data read operations from signals commonly available in microprocessor systems. Figure 6 shows the internal logic circuitry of the AD574A.The control signals CE, CS, and R/C control the operation of the converter. The state of R/C when CE and CS are both asserted determines whether a data read (R/C = 1) or a convert (R/C = 0) is in progress. The register control inputs AO and 12/8 control conversion length and data format. The AO line is usually tied to the least significant bit of the address bus. If a conversion is started with AO low, a full 12-bit conversion cycleis initiated. If AO is high during a convert start, a shorter 8-bit conversion cycle results. During data read operations, AO determines whether the three-state buffers containing the 8 MSBs of the conversion result (AO = 0) or the 4 LSBs (AO = 1) are enabled. The 12/8 pin determines whether the output data is to be organized as two 8-bit words (12/8 tied to DIGITAL COMMON) or a single 12-bit word (12/8 tied to VLOGIC). The 12/8 pin is not TTL-compatible and must be hard-wired to either VLOGIC or DIGITAL COMMON. In the 8-bit mode, the byte addressed when AO is high contains the 4 LSBs from the conversion followed by four trailing zeroes. This organization allows the data lines to be overlapped for direct interface to 8-bit buses without the need for external three-state buffers. It is not recommended that AO change state during a data read operation. Asymmetrical enable and disable times of the three-state buffers could cause internal bus contention resulting in potential damage to the AD574A.Figure4. AD574A Control LogicAn output signal, STS, indicates the status of the converter. STS goes high at the beginning of a conversion and returns low when the conversion cycle is complete.TIMINGThe AD574A is easily interfaced to a wide variety of microprocessors and other digital systems. The following discussion of the timing requirements of the AD574A control signals should provide the system designer with useful insight into the operation of the device.Figure 7 shows a complete timing diagram for the AD574A convert start operation. R/C should be low before both CE and CS are asserted; if R/C is high, a read operation will momentarily occur, possibly resulting in system bus contention. Either CE or CS may be used to initiate a conversion; however, use of CE is recommended since it includes one less propagation delay than CS and is the faster input. In Figure 7, CE is used to initiate the conversion.Figure 5Once a conversion is started and the STS line goes high, convert start commands will be ignored until the conversion cycle is complete. The output data buffers cannot be enabled during conversion.Figure 8 shows the timing for data read operations. During data read operations, access time is measured from the point where CE and R/C both are high (assuming CS is already low). If CS is used to enable the device, access time is extended by 100 ns.Figure6. Read Cycle TimingIn the 8-bit bus interface mode (12/8 input wired to DIGITAL COMMON), the address bit, AO, must be stable at least 150 ns prior to CE going high and must remain stable during the entire read cycle. If AO is allowed to change, damage to the AD574A output buffers may result.“STAND-ALONE” OPERATIONThe AD574A can be used in a “stand-alone” mode, which is useful in systems with dedicated input ports available and thus not requiring full bus interface capability. In this mode, CE and 12/8 are wired high, CS and AO are wired low, and conversion is controlled by R/C. The three-state buffers are enabled when R/C is high and a conversion starts when R/C goes low. This allows two possible control signalsa high pulse or a low pulse. Operation with a low pulse is shown in Figure 11. In this case, the outputs are forced into the high impedance state in response to the falling edge of R/C and return to valid logic levels after the conversion cycle is completed. The STS line goes high 600 ns after R/C goes low and returns low 300 ns after data is valid.Figure 7. Low Pulse for R/COutputs Enabled After ConversionIf conversion is initiated by a high pulse as shown in Figure 12, the data lines are enabled during the time when R/C is high. The falling edge of R/C starts the next conversion, and the data lines return to three-state (and remain three-state) until the next high pulse of R/C.Figure 8. High Pulse for R/COutputs Enabled While R/C High, Otherwise High-ZUsually the low pulse for R/C stand-alone mode will be used. Figure 13 illustrates a typical stand-alone configuration for 8086 type processors. The addition of the 74F/S374 latches improves bus access/release times and helps minimize digital feedthrough to the analog portion of the converter.INTERFACING THE AD574A TO MICROPROCESSORSThe control logic of the AD574A makes direct connection to most microprocessor system buses possible. While it is impossible to describe the details of the interface connections for every microprocessor type, several representative examples will be described here.GENERAL A/D CONVERTER INTERFACECONSIDERATIONSA typical A/D converter interface routine involves several operations. First, a write to the ADC address initiates a conversion.The processor must then wait for the conversion cycle to complete, since most ADCs take longer than one instruction cycle to complete a conversion. Valid data can, of course, only be read after the conversion is complete. The AD574A provides an output signal (STS) which indicates when a conversion is in progress. This signal can be polled by the processor by reading it through an external three-state buffer (or other input port). The STS signal can also be used to generate an interrupt upon completion of conversion, if the system timing requirements are critical (bear in mind that the maximum conversion time of the AD574A is only 35 microseconds) and the processor has other tasks to perform during the ADC conversion cycle. Another possible time-out method is to assume that the ADC will tak