基于FPGA设计的DDR接口注意事项.ppt

DDR/DDRIIThingstoconsider,Objectives,ThispresentationcoversaspectsnotaddressedinDDRSDRAMMegawizarddemonstration.AimstohelpanswersquestionslikeHowmanycontrollerscanIgetinthisdeviceWhatdoIneedtoconsideratlayoutWhatifIwanttorunbelow100orabove200MHzArethereadditionalconsiderationsforHardcopyWherecanIfindmoreinformationEtcetcUnfortunatelythisdoesmakethepresentation“bitty”.,WhatisDDR?(Brief)(Thissectionforthoseatthebeginningofthelearningcurve.),WhatisDDR,DDRstandsfor“doubledatarate”.GenerallywhenpeopletalkaboutDDRtheyaretalkingabouttransferringdatatoandfrommemory.DDRsimplymeansthereisdataonbothedgesofthestrobe.,DataStrobe(dqs),Data(dq),WhywouldIuseit?,Toincreaseyourbandwidthforthesamenumberofpins(comparedtoSDRAM).Andbecauseitischeap(commercialpartusedinPCs).Yourcustomersuseit.LookatthemarketshareofDDRandDDR2,Source:GartnerDataquest(May2004),Whatisinvolved?,Datapassesbackwardsandforwardsonahighspeedbi-directionbus.Adatastrobe(DQS)travelswiththedata.,DDR2Memory,MemoryController,On-ChipDLLPhaseShiftforDQSDelayCircuitry,t,DQ_i,DQS_i,DQ,DQS,DQS,Whatisinvolved,TheFPGAmustalignthedataandstrobe(dqanddqs)onthewayout(writes)anddelaythestrobe(dqs)by90degreesonthewayin(reads)tousedqsascapturestrobe.Theoperationclearlyinvolvesgoing“offchip”soweneedtobecarefuloftiminganalysis.Anditis(orcanbe)highspeedsoweneedtowatchoutforthingsliketermination.,WherecanIfindmoreinformation?(All:Rejoinpresentationhere),Whatcollateralalreadyexits?,TheMemorySolutionsWebpageontheAlterasite.HardwareboardssimulateyourdesignincludingPCBanddevicepackage.),BoardConsiderations,Micronhasalotofveryusefulmaterials,GeneralBoardGuidelines,Controlledimpedanceonsignallayers:Allsignalplanestobe50-ohmssingleendedimpedance+/-10%Allsignalplanestobe100-ohmsdifferentialimpedance+/-10%Componentplacement:BGAtoSurface-mountmusthaveminimum150-milclearance.Through-holetoSurface-mountonbottomsideclearancemustbegreaterthan200-mils.ViapadsRemovedunusedpadasthesecancauseadditionalunwantedcapacitance.,GeneralBoardDecoupling,Use0.1-Fcapacitorsinan0402/0603-sizedpackageProvidesufficientcapacitancewithoutaddingtoomuchinductanceMakeVTTvoltagedecouplingonboardclosetotheparallelpull-upresistors.ConnectthedecouplingcapacitorsbetweenVTTandground.ExampleTheCyclonememoryinterfaceboardhasa0.1-FcapacitorforeveryotherVTTpin.TheCyclonememoryinterfaceboardalsohas0.1-and0.01-FcapacitorsforeveryVDDandVDDQpin.,MemoryBoardPowerRouting,ExamplefromS2MB2:GND,3.3V,and1.2VareroutedasplanesThesesignalsareneededacrosstheboardVCCIOforthememoriesroutedinasinglesplitplanewith20-milgapsofseparationCanusejustpartoftheboardforeachmemoryVTTandQDRVCCINTareroutedasislandsor250-milpowertracesonsignallayersNotneededforanythingelseexcepttermination(forVTT)OscillatorsandPLLpowerareroutedasislandsor100-milpowertracesonsignallayersAgain,notneededforanythingelse,GeneralRoutingGuidelines,Alterarecommendsthatdesigners:Use45degreeangles(no90degreecorners)AvoidT-junctionsforcriticalnetsorclocks.AvoidT-junctionsgreaterthan250milsDisallowsignalsacrosssplitplanesRestrictroutingothersignalsclosetosystemresetsignalsAvoidroutingmemorysignalscloserthan0.025inchtoPCIorsystemclocks,RoutingGuidelines,ClockRoutingGuidelinesClocksshouldberoutedoninnerlayerswithouter-layerrunlengthsbeingheldtounder500milsThesesignalsshouldmaintaina10-milspacingfromothernetsDifferentialclocksshouldmaintainalength-matchingbetweenPandNsignalsof+/-15mils,routedinparallelDifferentialclockswithSMAsshouldrouteasadifferentialpairandbreak-outtoSMAsrightattheconnectorsSpacebetweenpairsshouldbeatleast3xthatusedbetweenthepairMustberouteddifferentially(5miltrace,10-15milspaceoncenters)andbeequaltoorupto100-milslongerthansignalsintheAddress/CommandGroup,RoutingGuidelines,FeedbackClockRoutingGuidelinesShouldbewithin100-milsoftheaveragelengthoftheByteLaneGroupsAddressandCommandRoutingGuidelinesAddress/CommandcanbeunbufferedorbufferedonDIMMUnbufferedaremoresusceptibletocrosstalkandaregenerallynosierthanbufferedUnbufferedshouldberoutedonadifferentlayerthanDQandDMandwithgreaterspacing,RoutingGuidelines,AllOtherRoutingGuidelinesAlldata,address,andcommandsignalsmusthavematchedlengthtraces+/-0.250inchesAllsignalswithinagiven“ByteLaneGroup”shouldbematchedlengthwithmaximumdeviationof+/-0.050inches.Allothersignalsaretomaintainaspacingthatisbasedonitsparallelismwithothernets:5milsforparallelruns0.5inches(1Xspacingrelativetoplanedistance)10milsforparallelrunsbetween0.5and1.0inches(2Xspacingrelativetoplanedistance)15milsforparallelrunsbetween1.0and6.0inches(3Xspacingrelativetoplanedistance),TerminationforMemories,ThepopularmemoriesvendorsdonotrequirecustomersadherestrictlytotheJEDECspecificationforterminationMemoryvendorsdoprovidesomesuggestedterminationschemesandresistancevalues.Pleasereferencethese.,TerminationforMemories,Terminationultimatelyneedtobechosenbyuserfortheirparticularboard.ThefollowingaresomeusefulguidelinesdependingonthefinalschemechosenWhenpull-upsareused,fly-byterminationconfigurationarerecommendedFly-byhelpsreducestubreflectionissuesDisadvantageiscomplexityofroutingandcostIfusingresistornetworksDonotshareR-packseriesresistorsbetweenaddress/commandanddatalines(DQ,DQS,DM)toeliminatecrosstalkwithinpackSeriesandpulluptolerances12%IfterminationresistorpacksusedDistancetoyourmemorydevice750milsDistancefromyourStratixdevice1250mils,BoardGuidelines,DonotforgettoreferencetheschematicsandgerberfilesthatalreadyexistfortheAlteraMemoryboards.,AlookatFrequency,OperationalFrequency,Below100MHzdevicethatsupportthisCyclone:CycloneII:Stratix:Recommenduseonnon-dqsmode.StratixII:Recommenduseonnon-dqsmode.Between101and199MHzCyclone:Upto133MHzoperationCycloneII:Upto166MHzoperationStratix:Upto200MHzinDQSmode.150MHzinnon-dqsmode.StratixII:Upto266MHzinDQSmode.150MHzinnon-dqsmode.Above200MHzStratixII:DDRIIoperation.UseofFed-backclockrecommended,Packagehasaneffect.,TakenfromAN348,TakenfromAN342,Tryingtorunbelow100MHz,GenerallyDDRSDRAMdevicesdonotrunbelow80MHz.StratixDLLfunctionsdownto100MHz,ForStratixcanusetheNon-DQSmode.Thatis,afreerunningcaptureclock,itisoftensimpler.,Un-checkthisboxfornon-dqsmode,Runningabove200MHz,DDRonlyspecedto200MHz(ieDDR400)soanythingaboveisDDRIIoperation.Timingisnowcritical(althoughalwaysimportantatanyfrequency)FedbackclockintroducedTocompensateforPVTvariationsinoutputbufferandtracklength.,Fittingacontrollerorcontrollersintoadevice,PinSelection,DQ/DQSpinsarefixedontheFPGAremovingmanyofthedifficult“bestplacement”choices.LeftwithfollowingpinselectionchoicesMemoryClocksUsematchedDDIOflopstocreateclocks?UsededicatedPLLoutputforclocking?DQ/DQSGroupsWhichgroupsshouldauserchoose?,PinSelectionMemoryClocks,AlterarecommendsusinggeneralpurposeDDIOratherthandedicatedplloutputclockAdvantagesUsingDDIOmimicsthewayDQS/DQaregenerated(allPVTvariationsaretracked)AlterahasthemostsystemtestdataforthisimplementationPreventanissueinmeetingtheTdqssrequirementoftheDDRspecification.(Thatis,relationshipbetweendqsandclock),PinSelection-DQ/DQSGroups,Largeinterfaces(e.g.x72)useupmostoralloftheDQ/DQSgroupsonthetoporbottomoftheFPGASmallerinterfacespresentachoicetotheuserofwhichgroupsarebesttouseAreanygroupsbettermatchedontheFPGA?Doanysetsofgroupsprovidebetterimmunitytonoise?,Howwideaninterface,Stratix:DQSmode:Stratixdeviceshaveuptoupto160dqpins.80ontopand80onbottom(checkspecificpackage)Non-dqsmodeanypincanbeusedbutlimitedto150MHzoperation.StratixII:DQSmode:SmallerpackageshavealownumberofdqspinssoifinterfacingtoaDIMMchecknumberofx8dqsgroupsfirst.Non-dqsmode:Asabove.Cyclone:8globalclocksinacyclone.2ofwhichareusedupintheAlteraDDRSDRAMIPcontroller.Thisleavesatotalof6globalclocks.DQSroutedonglobalclocklines.Thereforemaximumdatawidthforacycloneis48bits.(6*8=48)despitefactlargerpackageshave8dqspins.,Numberofcontrollersindevice,ApplicabletoStratix/GX+StratixIIDQSmodeThereare2DLLperdevice.1DLLcansupportNinterfaceifEnoughpinsAllinterfacesrunningatsamefreqencyStartixonly:TheDLLontop(orb