内容提要_20-13.ppt

VHDL3BASICOPERATORSANDARCHITECTUREBODY,Designdescriptions/=notequal=smaller,bigger,equaletc.,exercise3:VHDL(v.2b),5,Exercise3.1:Fillin“?_”.ItshowstheNAND-gateisnotassociative,soAnandBnandCisillegal.(AnandB)nandCAnand(BnandC),exercise3:VHDL(v.2b),6,StudentID:_Name:_Date:_(Submitthisattheendofthelecture.),ShiftoperatorsseeVHDLforEngineers(Googlebooks)KennethL.Short-2008-Computers-685,LogicalshiftandrotateSll(shiftleftlogical,fillblankwith0);srl(shiftrightlogical,fillblankwith0)rol(rotateleftlogical);ror(rotaterightlogical)circularoperation.E.g.“10010101”rol3is“10101100”Arithmeticshift(/wiki/Arithmetic_shift)sla(shiftleftarithmetic)fillblankwith0,sameassll(shiftleftlogical)sra(shiftrightarithmetic),fillblankwithsignbit(MSB),exercise3:VHDL(v.2b),7,Exercise3.2onshiftandrotate,A=“10010101”;Asll2=_Asrl3=_Asla3=_Asra2=_Arol3=_Aror5=_,exercise3:VHDL(v.2b),8,Somebasicoperators,+arithmeticadd,forinteger,float.-arithmeticsubtract,forinteger,float.2c:outstd_logic);3endand24architectureand2_archofand25begin6c=aandb;7endand2_arch,exercise3:VHDL(v.2b),16,Step2:Createcomponent“and2”basedon“entityand2”,10componentand211port(a,b:instd_logic;coutstd_logic);12-notesequenceofa,b,c13endcomponent14-nowuseitin“portmap”instructions,exercise3:VHDL(v.2b),17,Step3:connectcomponentsusingportmap,-assumeand2,or2areuserdefinedcomponents21architecturestruct_abcofabcxis22begin23label_u0:or2portmap(a,b,x);24label_u1:and2portmap(c,x,y);25endstruct_abc;26-label_u0,label_u1arelinelabels.,exercise3:VHDL(v.2b),18,a,c,x,y,b,Whatwillhappenifthese2linesareinterchanged?,Coreofthestructuraldesign,21architecturestruct_abcofabcxis22begin23label_u1:and2portmap(c,x,y);24label_u0:or2portmap(a,b,x);25endstruct_abc;,exercise3:VHDL(v.2b),19,Label_u0,label_u1arelinelabels“portmap”arereservedwords,linescanbeinterchanged,Exercise:3.3:,(a)Whenwillline23and24beexecuted?Answer:_(b)DrawtheschematicdiagramifaVHDLprogramhaslines23label_u0:and2portmap(a,c,x);24label_u1:or2portmap(b,x,y);(c)Completeline23and24ifthecircuitis23label_u0:?_24label_u1:?_,exercise3:VHDL(v.2b),20,a,c,x,y,b,entitytest_andor2is-Adetailedexampleport(in1:inSTD_LOGIC;in2:inSTD_LOGIC;in3:inSTD_LOGIC;out1:outSTD_LOGIC);endtest_andor2;architecturetest_andor2_archoftest_andor2iscomponentand2port(a,b:instd_logic;c:outstd_logic);endcomponent;componentor2port(a,b:instd_logic;c:outstd_logic);endcomponent;signalcon1_signal:std_logic;beginlabel1:and2portmap(in1,in2,con1_signal);label2:or2portmap(con1_signal,in3,out1);endtest_andor2_arch;,exercise3:VHDL(v.2b),21,in1,in3,out1,in2,Con1_signal,Exercise3.4Drawtheschematicdiagramofthehalf-adderbasedonarchitecturestruct_abcentityhalf_adderis-anotherexampleport(a:inbit;b:inbit;sum:outbit;carry:outbit);endhalf_adder;architecturehalf_adder_archofhalf_adderiscomponentxor2port(x,y:inbit;z:outbit);endcomponent;componentand2port(l,m:inbit;n:outbit);endcomponent;beginlabel1:xor2portmap(a,b,sum);label2:and2portmap(a,b,carry);endhalf_adder_arch;,exercise3:VHDL(v.2b),22,(2)Dataflowdesigndescriptionmethod,exercise3:VHDL(v.2b),23,Dataflow:concurrentexecution,1entityeqb_comp4is2port(a,b:instd_logic_vector(3downto0);3equals,bigger:outstd_logic);4endeqb_comp4;5architecturedataflow4ofeqb_comp4is6begin7equalsb)else0;-concurrent10enddataflow4;,exercise3:VHDL(v.2b),24,Exercise:3.5:Exercisebasedonentityeqb_comp4,1entityeqb_comp4is2port(a,b:instd_logic_vector(3downto0);3equals,bigger:outstd_logic);4endeqb_comp4;5architecturedataflow4ofeqb_comp4is6begin7equalsb)else0;-concurrent10enddataflow4;(a)Whenwilllines7,8beexecuted?Answer:_,exercise3:VHDL(v.2b),25,Exercise3.6:Drawtheschematicofthiscode,EntityabcisPort(a,b,c:instd_logic;youtstd_l;ogic);endabc;Architectureabc_archofabcissignalx:std_logic;Beginx=anorb;y=xandc;endabc_arch;,exercise3:VHDL(v.2b),26,(3)BehavioraldesigndescriptionmethodUsingProcess(),exercise3:VHDL(v.2b),27,Behavioraldesignissequentialthekeywordisprocess,Sequential,insideaprocessJustlikeasequentialprogramthemaincharacterisprocess(sensitivitylist),exercise3:VHDL(v.2b),28,1entityeqcomp4isport(2a,b:instd_logic_vector(3downto0);3equals:outstd_logic);4endeqcomp4;5architecturebehavioralofeqcomp4is6begin7comp:process(a,b)8begin9ifa=bthen10equals=1;11else12equals=0;13endif;14endprocess;15endbehavioral;,exercise3:VHDL(v.2b),29,Behavioraldesign:Itissequential,thekeywordisprocess,sequentialexecutionlikeasequentialsoftwareprogram,Exercise3.7:Exercisebasedoneqcomp4,(a)Whenwillline7,theprocess(),beexecuted?Answer:_(b)Whenwillline9,10beexecuted?Answer:_,1entityeqcomp4isport(2a,b:instd_logic_vector(3downto0);3equals:outstd_logic);4endeqcomp4;5architecturebehavioralofeqcomp4is6begin7comp:process(a,b)8begin9ifa=bthen10equals=1;11else12equals=0;13endif;14endprocess;15endbehavioral;,exercise3:VHDL(v.2b),30,ConcurrentVSsequential,Everystatementinsidethearchitecturebodyisexecutedconcurrently,exceptstatementsenclosedbyaprocess.ProcessStatementswithinaprocessareexecutedsequentially.Resultisknownwhenthewholeprocessiscomplete.Youmaytreataprocessasoneconcurrentstatementinthearchitecturebody.Process(sensitivitylist):whenoneormoresignalsinthesensitivitylistchangestate,theprocessexecutesonce.,exercise3:VHDL(v.2b),31,DESIGNCONSTRUCTIONS,Concurrentandsequential,exercise3:VHDL(v.2b),32,Designconstructions,Concurrent:statementsthatcanbestand-aloneWhen-elseWith-select-whenSequential:statementsthatcanonlyliveinsideprocessesCase-whenforin-to-loopIf-then-else,exercise3:VHDL(v.2b),33,sequential-withprocesses,Concurrentsequential-NOprocess,DesignconstructionsConcurrentstatements,exercise3:VHDL(v.2b),34,Concurrent:statementsthatcanstand-alone,(concurrent1)when-else(concurrent2)with-select-when,exercise3:VHDL(v.2b),35,concurrent-noprocess,When-else:exampleand-gate,1entitywhen_exis2port(in1,in2:instd_logic;3out1:outstd_logic);4endwhen_ex;56architecturewhen_ex_aofwhen_exis7begin8out1=1whenin1=1andin2=1else0;9endwhen_ex_a;,exercise3:VHDL(v.2b),36,concurrent-1-(when),And-gate,in1,in2,out,With-select-when:exampleand-gateagain,1entitywith_exis2port(in1,in2:instd_logic;3out1:outstd_logic);4endwith_ex;5architecturewith_ex_aofwith_exis6begin7within1select8out1=in2when1,-meanswhenin1=190whenothers;-othercases10endwith_ex_a;,exercise3:VHDL(v.2b),37,concurrent-2(with),And-gate,in1,in2,out,DesignconstructionsSequentialstatements,exercise3:VHDL(v.2b),38,Process(sensitivitylistofsignals)forsequentialexecution,1architecturefor_ex_archoffor_exis2begin3process(in1,in2)-executeoncewhenthesignals4-inthesensitivitylist(I.e.in1orin2)changestate5begin6out1=in1andin2;7:8endprocess;9out2out1out1=1;10out2=0;11endcase;12endprocess;13b”means“implies”not“bigger”allcasesmustbepresent,useotherstocompleteallcasesans:,exercise3:VHDL(v.2b),42,b(0),b(1),out1,out2,Ex-nor,For-in-to-loop(exampleinvert4inputs),1architecturefor_ex_archoffor_exis2begin3process(in1)4begin5label_for0:foriin0to3loop6out1(i)=notin1(i);7endloop;8endprocess;9endfor_ex_arch;,exercise3:VHDL(v.2b),43,in(3:0),out(3:0),Exercise3.9:useofFOR,Rewritearch1withoutaprocess().1architecturearch1ofex1is2begin3456789endfor_ex_arch;,1architecturearch1ofex1is2begin3process(in1)4begin5lab0:foriin0to3loop6out1(i)=notin1(i);7endloop;8endprocess;9endfor_ex_arch;,exercise3:VHDL(v.2b),44,?,If-then-else:exampleand,1architectureif_ex_aofif_exis2begin3process(in1,in2)4begin5ifin1=1andin2=1then6out1=1;7else8out1=0;9endif;10endprocess;11endif_ex_a;,exercise3:VHDL(v.2b),45,And-gate,in1,out,in2,sequential-3if-then-else,Useofsignalsandvariables,Signals(global)Variable(liveinsideprocessesonly)WewilllearnmoreaboutthisinFinitestatemachinesd