Modelsim仿真risk cpu

实验报告分组信息：组长成员一， 实验内容CPU的验证，使用cpu_test.v作为测试程序。其子模块包括寄存器，计数器，存储器，多路选择器，时序控制，算术逻辑单元等的设计二， 实验目的用诊断程序作为激励，在子模块全部完成的情况下，测试所设计的CPU三， 实验工具本次试验中，使用两个软件平台：Quartus II 11.0和Modelsim SE 10.2c四， 实验说明我们在本次实验中，采用的仿真方法是结合Quartus II和Modelsim两个软件。因为对于代码较杂，需引入较多外部测试文件的工程而言，ModelSim的响应时间长，窗口初始化慢。结合使用两个软件，可在Quartus II中调用ModelSim软件。Quartus II作为FPGA的软件平台，在建立大型工程方面自然有ModelSim无法比拟的优势。在Quartus II中编写代码可以很方便地进行编译查错，生成对应的模块，在.bdf文件中进行模块的连线或者在.v文件中进行实例化等，而且Quartus II本身提供逻辑分析仪，也可以脱离ModelSim进行初步的波形仿真和校验。因而本实验中，我们采用的两个软件相结合的仿真方法。模块名Alu设计测试模块说明：1ALU 端口信息如上面的电路图；2ALU 的设计同时还要满足下面的规则：模块名为alu;ALU 为组合逻辑，输入变化立刻就会引起输出的相应变化。操作码和操作数的变化会引起信号alu_out 的变化，中间有3.5ns 的延迟。操作码为3 位，功能如下：Opcode : ALU Operation000 : pass accumulator001 : pass accumulator010 : ADD (data + accumulator)011 : AND (data & accumulator)100 : XOR (data accumulator)101 : pass data110 : pass accumulator111 : pass accumulator操作码为X 时，ALU 的输出也为不定态。累加器accum 的变化会引起零标志位（zero）的变化，中间有1.2ns 的延迟。当累加器为0 时zero = 1,其他情况为0。设计代码：timescale 1ns / 100psmodule alu(alu_out, zero, opcode, data, accum); input 7:0 data, accum; input 2:0 opcode; output 7:0 alu_out; reg 7:0 alu_out; output zero; reg zero; always (data or accum or opcode) casez(opcode) 3b000: #3.5 alu_out=accum; 3b001: #3.5 alu_out=accum; 3b010: #3.5 alu_out=accum+data; 3b011: #3.5 alu_out=accum&data; 3b100: #3.5 alu_out=accumdata; 3b101: #3.5 alu_out=data; 3b110: #3.5 alu_out=accum; 3b111: #3.5 alu_out=accum; default: #3.5 alu_out=bx; endcase always (accum) if(accum=0) #1.2 zero=1b1; else #1.2 zero=1b0;endmodule测试代码如下：timescale 1ns / 1nsmodule alu_test; wire 7:0 alu_out; reg 7:0 data, accum; reg 2:0 opcode; integer i, err_cnt;/ Instantiate the ALU. Named mapping allows the designer to have freedom/ with the order of port declarations alu alu1 (.alu_out(alu_out), .zero(zero), /outputs from ALU .opcode(opcode), .data(data), .accum(accum); /inputs to ALU /define mnemonics to represent opcodes define PASSA 3b000, 3b001, 3b110, 3b111 define ADD 3b010 define AND 3b011 define XOR 3b100 define PASSD 3b101/ Define a safe delay between each strobing of the ALU inputs/outputs define strobe 20 initial begin / SET UP THE OUTPUT FORMAT FOR THE TEXT DISPLAY $display(ttt INPUTS OUTPUTS n); $display(ttt OPCODE DATA IN ACCUM IN | ALU OUT ZERO BIT); $display(ttt - - - | - -); $timeformat(-9, 1, ns, 9); /Display time in nanoseconds err_cnt = 0; / APPLY STIMULUS TO THE INPUT PINS accum = 8hDA; /Initialize inputs to the ALU data = 8h37; for (i = 0; i = 7; i = i+1) /VERIFY OPERATION FOR ALL 8 OPCODES begin /change inputs at strobe point #strobe opcode = i; /Wait for ALU to process inputs #(strobe/4) check_outputs; /call a task to verify outputs end /VERIFY OPERATION WITH UNKNOWN OPCODE #(3*strobe/4) opcode = 3b00x; #(strobe/4) check_outputs; /VERIFY OPERATION OF ZERO BIT #(3*strobe/4) accum = 8h00; opcode = ADD; #(strobe/4) check_outputs; /WAIT 1 MORE STROBE AND THEN FINISH #strobe if (err_cnt) $display(nThere were %d errors in all.n, err_cnt); else $display(nNo errors were found!n); $finish; end task check_outputs; casez (opcode) PASSA : begin $display(PASS ACCUM OPERATION:, %b %b %b | %b %b, opcode, data, accum, alu_out, zero); if (alu_out != accum) | (zero != !accum) error; end ADD : begin $display(ADD OPERATION :, %b %b %b | %b %b, opcode, data, accum, alu_out, zero); if (alu_out != (accum + data) | (zero != !accum) error; end AND : begin $display(AND OPERATION :, %b %b %b | %b %b, opcode, data, accum, alu_out, zero); if (alu_out != (accum & data) | (zero != !accum) error; end XOR : begin $display(XOR OPERATION :, %b %b %b | %b %b, opcode, data, accum, alu_out, zero); if (alu_out != (accum data) | (zero != !accum) error; end PASSD : begin $display(PASS DATA OPERATION :, %b %b %b | %b %b, opcode, data, accum, alu_out, zero); if (alu_out != data) | (zero != !accum) error; end default : begin $display(UNKNOWN OPERATION :, %b %b %b | %b %b, opcode, data, accum, alu_out, zero); if (alu_out != 8bx) | (zero != !accum) error; end endcase endtask task error; begin $display(ttt ERROR AT %t, EXPECTED : %b %bn, $realtime, 8bx, !accum); err_cnt = err_cnt + 1; end endtaskendmodule测试结果：测试分析：可以看到opcode为010时，alu_out = 00110111 + 110111010 = 00010001, opcode为011时，alu_out = 00110111& 110111010 = 00010010, opcode为100时，alu_out = 00110111 110111010= 11101101, 依次验证，可以看出得到的结果均正确。测试成功，alu功能正常。模块名mem设计测试模块说明：1存储器设计规则如下：模块名为memory。存储字最高位是bit 7,最低位是bit 0。第一个地址是0，最后一个是31。存取memory 是异步的，通过两个信号read 和write 来控制，读写控制如下。在write 信号的上升沿，数据总线的数据被写入由地址总线（addr）寻址的memory 单元。在read 信号有效（为1）时，由地址总线寻址的memory 单元内容被输出到数据总线。在read 信号无效期间，数据总线被拉为高阻。设计代码：/* * Model of RAM Memory */timescale 1ns / 1nsmodule mem(data,addr,read,write); inout 7:0 data; input 4:0 addr; input read, write; reg 7:0 memory 31:0; /定义存储空间 always (posedge write) begin memoryaddr=data7:0; /write上升沿时向memory写入数据 end assign data=(read=1)?memoryaddr:8bz; /data为线性变量，应使用连续赋值endmodule测试代码/* * Stimulus for the RAM model */timescale 1ns / 1nsmodule memtest; reg read, write; reg 4:0 addr; wire 7:0 data; reg 7:0 expected; integer error_cnt; reg 7:0 data_reg; /SHADOW REGISTER FOR PROCEDURAL ASSIGNMENTS assign data = (!read)?data_reg:8bz; /TRANSFER SHADOW REGISTER TO DATA BUS mem m1(data,addr,read,write); task write_val; begin #1 write = 1; / let address lines settle, then set write high #1 write = 0; / after 1ns, set write low end endtask task check_data; #1 if (data != expected) / Check data begin $display(* ERROR at time %t! read back %h from address %h:, $realtime, data, addr, Expected to read %h, expected); error_cnt = error_cnt + 1; end endtask initial begin $timeformat(-9, 1, ns, 9); /display time in nanoseconds/ Initialize all variables data_reg = 8h0; /ASSIGN VALUE TO SHADOW REGISTER error_cnt = 0; write = 0; read = 0; addr = 0;/ Initialize mem to all zeroes $display(n Setting all memory cells to zero.%t,$stime); repeat (32) beginwrite_val; addr = addr + 1; / Step through all 32 memory locations end/ Read back a zero from memory $display(n Reading from one memory address.%t,$stime); #10 addr = 5h0A; / Read from the 10th word in memory read = 1; expected = 8h00; / Data should be all zeroes check_data; #9 read = 0;/ Set mem to alternating patterns $display(n Setting all memory cells to alternating patterns.%t,$stime); #10 addr = 0; data_reg = 8hAA; /ASSIGN VALUES TO SHADOW REGISTER repeat (32) beginwrite_val;addr = addr + 1; / Step through all 32 memory locationsdata_reg = data_reg; /ASSIGN VALUES TO SHADOW REGISTER end/ Read back alternating patterns from five consecutive memory locations $display(n Doing block read from five memory addresses.%t,$stime); #10 expected = 8h55; read = 1; for (addr = 5h05; addr = 5h09; addr = addr + 1) begincheck_data;expected = expected; / Alternate between checking for AA and 55 end read = 0; $display(n Completed Memory Tests With %0d Errors!n, error_cnt); $stop; $finish; end endmodule测试结果：测试分析：测试表明，各阶段测试值与期望值相等，没有error出现。测试成功，mem功能正常。模块名register设计测试模块说明：1、寄存器可用来实例累加器（ACCUMULATOR）和指令寄存器（InstructionRegister）;2、rst 为低电平复位，复位时寄存器输出清零；3、ena 为使能信号，ena 为1 时，在clk 上升沿data 的值将被存入，ena 为0时，寄存器输出保持不变。设计代码：/* * 8-bit register */timescale 1 ns / 100 psmodule register(r, clk, data, ena, rst); output 7:0 r; input 7:0 data; input clk, ena, rst; reg 7:0 r ; always (posedge clk) begin if(!rst)r7:0=8b0; /同步复位 else if(ena)r7:0=data7:0; /同步赋值 endendmodule测试代码/* * Stimulus for testing the 8-bit Register */timescale 1 ns / 100 psmodule test; wire 7:0 reg_out; /declare vector for register output reg 7:0 data; reg ena, rst; register r1(reg_out, clk, data, ena, rst); clock c1 (clk); /clock oscilator initial /display inputs & outputs as waveform begin #100 $finish; end/* SPECIFY INPUT STIMULI */ initial begin/ initialize inputs rst = 1; ena = 0; data = 8h5f; / Output should be unknown/ test that reset works #5 rst = 0; ena = 1; / Output should go to zero/ test that enable works #15 rst = 1; / Output should be clocked from data #20 data = 8h3d; #20 ena = 0; data = 8h19; / Output should not be clocked from data. endendmodule测试结果：测试分析：初始时，置位和复位信号均无效，输出为不定态X5个时间单位后，复位信号有效，输出清零再经过15个时间单位，复位信号消失，置位信号有效，30单位时间的时钟上升沿到达后，data的值赋给out40单位时间时，data的值发生变化，此时置位信号仍有效，因此50单位时间的时钟上升沿到达后，out的值被更新60单位时间时，置位信号失效，因此之后输出不再变化。测试成功，register功能正常。模块名Controller设计测试模块说明：时序控制器与时钟的上升沿同步产生8 个节拍，这8 个节拍构成一个指令周期。每条指令的取指和执行在8 个节拍完成，前半个指令周期进行取指操作，后半个指令周期指令执行操作。操作码与指令的对应关系：设计代码：timescale 1ns / 1nsmodule control(rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel, opcode, zero, clk, rst); output rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel; input 2:0 opcode; input zero, clk, rst; reg rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel; parameter HLT=3b000;/? parameter SKZ=3b001; parameter ADD=3b010; parameter AND=3b011; parameter XOR=3b100; parameter LDA=3b101; parameter STO=3b110; parameter JMP=3b111; reg2:0 state;/? always(posedge clk or negedge rst) begin if(!rst) begin state = 3b000; rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b000000000; end else case(state) 3b000:begin state=3b001; rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b000000001; end/rest 3b001:begin state=3b010; rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b100000001; end/address setup1 3b010:begin state=3b011; rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b101000001; end/instruction fetch 3b011:begin state=3b100; rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b101000001; end/idle 3b100:begin state=3b101; if(opcode=HLT) rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b000001100;/address setup2 else rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b000001000; end 3b101:begin state=3b110; /operand fetch if(opcode=ADD|opcode=AND|opcode=XOR|opcode=LDA) rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b100000000; else rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b000000000; end 3b110:begin state=111; if(opcode=SKZ&zero=1b1) rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b000001010; else begin if(opcode=ADD|opcode=AND|opcode=XOR|opcode=LDA) rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b100000000; else begin if(opcode=JMP) rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b000010010; else rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b000000010; end end end 3b111:begin state=3b000; if(opcode=SKZ&zero=1b1) rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b000001010; else begin if(opcode=ADD|opcode=AND|opcode=XOR|opcode=LDA) rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b100100000; else begin if(opcode=STO) rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b010000010; else begin if(opcode=JMP)rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b000011010; else rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel=9b000000010; end end end end endcase end endmodule测试结果：波形图：测试代码运行结果：There were 0 errors detected.没有错误测试分析：测试代码：/* * Stimulus to test the Sequence Controller * * This module contains the following parts: * * A routine which reads stimulus from a test pattern file and compares * the simulation results to an expected results file. * */timescale 1ns / 1nsmodule controller_test; define period 10 define fetch_cycle 80 define setup_time 2 define prop_delay 6 /* time for changes on inputs to reach outputs */ define num_vectors 16 define num_results 128 define outs rd,wr,ld_ir,ld_acc,ld_pc,inc_pc,halt,data_e,sel reg 2:0 opcode; reg rst, zero, clk; reg 4:0 test_vectors 1:num_vectors; /arrays to hold pattern files reg(3*8):0 mnemonic; /reg to hold 3 8-bit ASCII character opcode mnemonic integer vector, num_errors; control i1(outs, opcode, zero, clk, rst);/* * Generate the clock */ initial begin clk=1; forever #(period/2) clk = !clk; end/* * Load in the test vector pattern file and apply each pattern to the * controller inputs. */ initial begin num_errors = 0; $timeformat(-9, 1, ns, 9); /display time in nanoseconds $readmemb(test_vectors.pat, test_vectors); /load input vector file rst, zero, opcode = test_vectors1; /apply 1st test vector #(fetch_cycle -setup_time) / synch to just before a fetch cy