基于FPGA数字锁相环源程序代码(已验证运行-超值)

基于FPGA数字锁相环源程序代码（已验证运行，超值）module dpll_top (fin,fout,clk,reset,Kmode);input fin,clk; /clk时钟100ns(10MHZ）input reset; /reset高电平复位，enable高电平有效input 2:0 Kmode; /滤波计数器的计数模值设定output fout; /fout是锁频锁相输出reg fout;reg 8:0 Ktop; reg 8:0Count;wire inc,dec;reg dnup;reg inc_new,dec_new,inc_pulse,dec_pulse;reg delayed,advanced,Tff;reg IDout;reg 14:0 count_N; reg 15:0 cnt; reg cnt_en;reg load;wire cnt_clr;/2.异或门鉴相器模块always (fin or fout)begin dnup=finfout;end /3.K模计数器模块always (Kmode) begin case(Kmode) 3b001:Ktop=7; 3b010:Ktop=15; 3b011:Ktop=31; 3b100:Ktop=63; 3b101:Ktop=127; 3b110:Ktop=255; 3b111:Ktop=511; default:Ktop=15; endcase end /根据鉴相器输出的加减控制信号dnup进行可逆计数器的加减运算always (posedge clk or posedge reset)begin if(reset) Count=0; else if(!dnup) begin if(Count=Ktop) Count=0; else Count=Count+1; end else begin if(Count=0) Count=Ktop; else Count=Count-1; end end /输出进位脉冲carry和借位脉冲borrowassign inc=!dnup&(Count=Ktop);assign dec=dnup&(Count=0);/4.脉冲增减模块always (posedge clk)begin if(!inc) begin inc_new=1; inc_pulse=0; end else if (inc_pulse) begin inc_new=0; inc_pulse=0; end else if (inc&inc_new) begin inc_pulse=1; inc_new=0; end else begin inc_pulse=0; inc_new=0; endend always (posedge clk)begin if(!dec) begin dec_new=1; dec_pulse=0; end else if (dec_pulse) begin dec_new=0; dec_pulse=0; end else if (dec&dec_new) begin dec_pulse=1; dec_new=0; end else begin dec_pulse=0; dec_new=0; endend always(posedge clk)begin if (reset) begin Tff=0; delayed=1;advanced=1; end else begin if (inc_pulse) begin advanced=1;Tff=!Tff; end else if(dec_pulse) begin delayed=1; Tff=!Tff; end else if (Tff=0) begin if(!advanced) Tff=!Tff; else if(advanced) begin Tff=Tff; advanced=0; end end else begin if (!delayed) Tff=!Tff; else if(delayed) begin T