tina_ti_spice_modelsdrv8301drv8301_tina-ti_spice_modeldocuments

1、Sample & BuySupport & CommunityReference DesignProduct FolderTechnical DocumentsTools & SoftwareDRV8301SLOS719F AUGUST 2011 REVISED JANUARY 2016DRV8301 Three-Phase Gate Driver With Dual Current Shunt Amplifiersand Buck Regulator1Features6-V to 60-V Operating Supply Voltage Range 1.7-A Source and 2.3

2、-A Sink Gate Drive Current CapabilitySlew Rate Control for EMI Reduction Bootstrap Gate Driver With 100% Duty Cycle Support6- or 3-PWM Input ModesDual Integrated Current Shunt Amplifiers With Adjustable Gain and OffsetIntegrated 1.5-A Buck Converter 3.3-V and 5-V Interface Support SPIProtection Feat

3、ures:3 DescriptionThe DRV8301 is a gate driver IC for three-phase motor drive applications. The device provides three half-bridge drivers, each capable of driving two N- channel MOSFETs. The DRV8301 supports up to 1.7- A source and 2.3-A peak current capability. The DRV8301 can operate off of a sing

4、le power supply with a wide range from 6-V to 60-V. The device uses a bootstrap gate driver architecture with trickle charge circuitry to support 100% duty cycle. The DRV8301 uses automatic handshaking when the high-side or low-side MOSFET is switching to prevent flow of current. Integrated VDS sens

5、ing of the high-side and low-side MOSFETs is used to protect the external power stage aga t overcurrent conditions.The DRV8301 includes two current shunt amplifiers for accurate current measurement. The amplifiers support bidirectional current sensing and provide an adjustable output offset up to 3

6、V.The DRV8301 also includes an integrated switching mode buck converter with adjustable output and switching frequency. The buck converter can provide up to 1.5 A to support MCU or additional system power needs.The SPI provides detailed fault reporting and flexible parameter settings such as gain op

7、tions for the current shunt amplifiers and slew rate control of the gate drivers.Programmable Dead Time Control (DTC) Programmable Overcurrent Protection (OCP)PVDD and GVDD Undervoltage Lockout (UVLO)GVDD Overvoltage Lockout (OVLO)Overtemperature Warning/Shutdown (OTW/OTS)Reported Through nFAULT, nO

8、CTW, and SPI Registers2Applications3-Phase BLDC and PMSM Motors CPAPs and PumpsE-bikes Power ToolsRobotics and RC ToysIndustrial AutomationDevice Information(1)(1) For all available packages, see the orderable addendum at the end of the data sheet.Simplified Schematic6 to 60 VDRV8301PWMGate DriveSPI

9、3-Phase Brushless Pre-DriverDiff AmpsMSensenFAULTBuck ConverternOCTWVcc (Buck)An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use intellectual property matters and other important disclaimers. PRODUCTION DATA.afety-critical applications,MCUN-Channel MOSFE

10、TsPART NUMBERPACKAGEBODY SIZE (NOM)DRV8301HTSSOP (56)14.00 mm 8.10 mmDRV8301SLOS719F AUGUST 2011 REVISED JANUARY 2016Table of Contents123456Features1Applications1Description1Revision History2Pin Configuration and Functions3Specifications7.6Feature Description15Device Functional M

11、odes20Programming21Register Maps228Application and Implementation248.1 Application Information248.2 Typical Application25Power Supply Recommendations289.1 Bulk Capacitance28Layout2910.1 Layout Guidelines2910.2 Layout Example30Device and Documentation Support3Absolute Maxi

12、mum Ratings6ESD Ratings6Recommended Operating Conditions7Thermal Information7Electrical Characteristics8Current Shunt Amplifier Characteristics9Buck Converter Characteristics10SPI Timing Requirements (Slave Mode Only)10Gate Timing and Protection SwitchingCharacteristics11910111.411.5Doc

13、umentation Support31Community Resources31Trademarks31Electrostatic Discharge Caution31Glossary316.10 Typical Characteristics12Detailed Description137.1 Overview137.2 Functional Block Diagram147Mechanical, Packaging, and Orderable Information31124Revision HistoryNOTE: Page numbers for previous revisi

14、ons may differ from page numbers in the current version.Changes from Revision E (October 2015) to Revision FPage Changed VEN_BUCK in Buck Converter Characteristics From: MIN = 0.9 V and MAX = 1.55 V To: MIN = 1.11 V andMAX = 1.36 V.10Changes from Revision D (August 2015) to Revision EPageCorrected t

15、able note for dead time programming definition11Updated description of gate driver power-up sequencing errata24Fixed connections for pin 25 in Figure 725Changes from Revision C (January 2015) to Revision DPageVPVDD absolute max voltage rating reduced from 70 V to 65 V6Clarification made on how the O

16、CP status bits report in Overcurrent Protection and Reporting (OCP)17Update to PVDD1 undervoltage protection in Undervoltage Protection (PVDD_UV and GVDD_UV) describingspecific transient brownout issue.18Update to EN_GATE pin functional description in EN_GATE clarifying proper EN_GATE reset pulse le

17、ngths.20Added gate driver power-up sequencing errata24Added Community Resources31Changes from Revision B (August 2013) to Revision CPage Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementationsection, Power Supply Recommendations section, Layout

18、section, Device and Documentation Support section, andMechanical, Packaging, and Orderable Information section62Submit Documentation FeedbackCopyright 20112016, Texastruments IncorporatedProduct Folder Links: DRV8301DRV8301SLOS719F AUGUST 2011 REVISED JANUARY 20165Pin Configuration and Fun

19、ctionsDCA Package56-Pin HTSSOP with PowerPAD Top ViewRT_CLK COMP VSENSE PWRGD nOCTWnFAULTDTC nSCS SDI SDOSCLK DC_CAL GVDD CP1 CP2 EN_GATEINH_A INL_A INH_B INL_B INH_C INL_C DVDD REF SO1 SO2 AVDDAGNDSS_TR EN_BUCK PVDD2 PVDD2 BST_BK PHPH VDD_SPI BST_A GH_A SH_A GL_A SL_A BST_B GH_B SH_B GL_B SL_B BST_

20、C GH_C SH_C GL_C SL_C SN1 SP1 SN2 SP2PVDD1 1 56 5 52 25 32 Pin Functions(1)KEY: I =Input, O = Output, P = PowerSubmit Documentation Feedback3Copyright 20112016, Texastruments IncorporatedProduct Folder Links: DRV8301GND (57) - PWR_PADPINTYPE(1)DESCRIPTIONNAMENO.RT_CLK1IResistor timing and external c

21、lock for buck regulator. Resistor should connect to GND (PowerPAD) with very short trace to reduce the potential clock jitter due to noise.COMP2OBuck error amplifier output and input to the output switch current comparator.VSENSE3IBuck output voltage sense pin. Inverting node of error amplifier.PWRG

22、D4OAn open-drain output with external pullup resistor required. Asserts low if buck output voltage is low due to thermal shutdown, dropout, overvoltage, or EN_BUCK shut downnOCTW5OOvercurrent and/or overtemperature warning indicator. This output is open drain with external pullup resistor required.

23、Programmable output mode via SPI registers.nFAULT6OFault report indicator. This output is open drain with external pullup resistor required.DTC7IDead-time adjustment with external resistor to GNDnSCS8ISPI chip selectSDI9ISPI inputSDO10OSPI output313029262728515049484746454443424140393837363534336789

24、101112131415161718192021222324555453234DRV8301SLOS719F AUGUST 2011 REVISED JANUARY 2016Pin Functions (continued)4Submit Documentation FeedbackCopyright 20112016, Texastruments IncorporatedProduct Folder Links: DRV8301PINTYPE(1)DESCRIPTIONNAMENO.SCLK11ISPI clock signalDC_CAL12IWhen DC_CAL i

25、s high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset calibration can be done through external microcontroller.GVDD13PInternal gate driver voltage regulator. GVDD cap should connect to GNDCP114PCharge pump pin 1, ceramic capacitor should be used between CP1 and CP2CP215PC

26、harge pump pin 2, ceramic capacitor should be used between CP1 and CP2EN_GATE16IEnable gate driver and current shunt amplifiers. Control buck through EN_BUCK pin.INH_A17IPWM input signal (high side), half-bridge AINL_A18IPWM input signal (low side), half-bridge AINH_B19IPWM input signal (high side),

27、 half-bridge BINL_B20IPWM input signal (low side), half-bridge BINH_C21IPWM input signal (high side), half-bridge CINL_C22IPWM input signal (low side), half-bridge CDVDD23PInternal 3.3-V supply voltage. DVDD cap should connect to AGND. This is an output, but not specified to drive external circuitry

28、.REF24IReference voltage to set output of shunt amplifiers with a bias voltage which equals to half of the voltage set on this pin. Connect to ADC reference in microcontroller.SO125OOutput of current amplifier 1SO226OOutput of current amplifier 2AVDD27PInternal 6-V supply voltage, AVDD cap should al

29、ways betalled and connected to AGND. This is an output, but not specified to drive external circuitry.AGND28PAnalog ground pin. Connect directly to GND (PowerPAD).PVDD129PPower supply pin for gate driver, current shunt amplifier, and SPI communication. PVDD1 is independent of buck power supply, PVDD

30、2. PVDD1 cap should connect to GNDSP230IInput of current amplifier 2 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best common mode rejection.SN231IInput of current amplifier 2 (connecting to negative input of amplifier).SP132IInput of

31、 current amplifier 1 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best common mode rejection.SN133IInput of current amplifier 1 (connecting to negative input of amplifier).SL_C34ILow-Side MOSFET source connection, half-bridge C. Low-s

32、ide VDS measured between this pin and SH_C.GL_C35OGate drive output for low-side MOSFET, half-bridge CSH_C36IHigh-side MOSFET source connection, half-bridge C. High-side VDS measured between this pin and PVDD1.GH_C37OGate drive output for high-side MOSFET, half-bridge CBST_C38PBootstrap cap pin for

33、half-bridge CSL_B39ILow-side MOSFET source connection, half-bridge B. Low-side VDS measured between this pin and SH_B.GL_B40OGate drive output for low-side MOSFET, half-bridge BSH_B41IHigh-side MOSFET source connection, half-bridge B. High-side VDS measured between this pin and PVDD1.GH_B42OGate dri

34、ve output for high-side MOSFET, half-bridge BBST_B43PBootstrap cap pin for half-bridge BSL_A44ILow-side MOSFET source connection, half-bridge A. Low-side VDS measured between this pin and SH_A.GL_A45OGate drive output for low-side MOSFET, half-bridge ASH_A46IHigh-side MOSFET source connection, half-

35、bridge A. High-side VDS measured between this pin and PVDD1.GH_A47OGate drive output for high-side MOSFET, half-bridge ADRV8301SLOS719F AUGUST 2011 REVISED JANUARY 2016Pin Functions (continued)Submit Documentation Feedback5Copyright 20112016, Texastruments IncorporatedProduct Folder Links:

36、 DRV8301PINTYPE(1)DESCRIPTIONNAMENO.BST_A48PBootstrap cap pin for half-bridge AVDD_SPI49ISPI supply pin to support 3.3-V or 5-V logic. Connect to the same supply that the MCU uses for SPI operation.PH50, 51OThe source of the internal high side MOSFET of buck converterBST_BK52PBootstrap cap pin for b

37、uck converterPVDD253, 54PPower supply pin for buck converter, PVDD2 cap should connect to GND.EN_BUCK55IEnable buck converter. Internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistorsSS_TR56IBuck soft-start and tracking. A

38、n external capacitor connected to this pets the output rise time. Because the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. Cap should connect to GNDGND(PowerPAD)57PGND pin. The exposed power pad must be electrically connected to ground plane throu

39、gh soldering to PCB for proper operation and connected to bottom side of PCB through vias for better thermal spreading.DRV8301SLOS719F AUGUST 2011 REVISED JANUARY 20166 Specifications6.1 Absolute Maximum Ratingssee (1)(1) Stresses beyond those listed under Absolute Maximum Ratings may caus

40、e permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device

41、reliability.6.2 ESD Ratings(1)(2)JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.6Submit Documentation FeedbackCopyright 20112016, Texa

42、struments IncorporatedProduct Folder Links: DRV8301VALUEUNITV(ESD)ElectrostaticdischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all p(1)2000VCharged device model (CDM), per JEDEC specification JESD22-C101, all p(2)500MINMAXUNITVPVDDSupply voltageRelative to PGND0.365VMaximum supply volta

43、ge ramp rateVoltage rising up to PVDDMAX1V/SVPGNDMaximum voltage between PGND and GND0.30.3VIIN_MAXMaximum current for all digital and analog inputs (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, SCLK, SCS, SDI, EN_GATE, DC_CAL, DTC)11mAISINK_MAXMaximum sinking current for open-drain p(nFAULT and nOCTW

44、P)7mAVOPA_INVoltage for SPx and SNx p0.60.6VVLOGICInput voltage range for logic/digital p(INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, EN_GATE, SCLK, SDI, SCS, DC_CAL)0.37VVGVDDMaximum voltage for GVDD pin13.2VVAVDDMaximum voltage for AVDD pin8VVDVDDMaximum voltage for DVDD pin3.6VVVDD_SPIMaximum volta

45、ge for VDD_SPI pin7VVSDOMaximum voltage for SDO pinVDD_SPI + 0.3VVREFMaximum reference voltage for current amplifier7VIREFMaximum current for REF pin100ATJMaximum operating junction temperature40150CTstgStorage temperature55150CDRV8301SLOS719F AUGUST 2011 REVISED JANUARY 20166.3Recommended

46、 Operating Conditions6.4Thermal Information(1)For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.Submit Documentation Feedback7Copyright 20112016, Texastruments IncorporatedProduct Folder Links: DRV8301THER

47、MAL METRIC(1)DRV8301UNITDCA (HTSSOP)56 PRJAJunction-to-ambient thermal resistance30.3C/WRJC(top)Junction-to-case (top) thermal resistance33.5C/WRJBJunction-to-board thermal resistance17.5C/WJTJunction-to-top characterization parameter0.9C/WJBJunction-to-board characterization parameter7.2C/WRJC(bot)

48、Junction-to-case (bottom) thermal resistance0.9C/WMINMAXUNITVPVDD1DC supply voltage PVDD1 for normal operationRelative to PGND660VVPVDD2DC supply voltage PVDD2 for buck converter3.560VIDIN_ENInput current of digital pwhen EN_GATE is high100AIDIN_DISInput current of digital pwhen EN_GATE is low1ACO_O

49、PAMaximum output capacitance on outputs of shunt amplifier20pFRDTCDead time control resistor range. Time range is 50 ns (-GND) to 500 ns (150 k) with a linear approximation.0150kIFAULTnFAULT pink current, open-drainV = 0.4 V2mAIOCTWnFAULT pink current, open-drainV = 0.4 V2mAVREFExternal voltage refe

50、rence voltage for current shunt amplifiers26VgateOperating switching frequency of gate driverQg(TOT) = 25 nC or total 30-mA gate drive average current200kHzIgateTotal average gate drive current30mATAAmbient temperature40125CDRV8301SLOS719F AUGUST 2011 REVISED JANUARY 20166.5 Electrical Cha

51、racteristicsPVDD = 6 to 60 V, TC = 25C, unless specified under test condition8Submit Documentation FeedbackCopyright 20112016, Texastruments IncorporatedProduct Folder Links: DRV8301PARAMETERTEST CONDITIONSMINTYPMAXUNITINPUT P: INH_X, INL_X, nSCS, SDI, SCLK, EN_GATE, DC_CALVIHHigh input threshold2VV

52、ILLow input threshold0.8VRPULL_DOWN INTERNAL PULLDOWN RESISTOR FOR GATE DRIVER INPUTSREN_GATEInternal pulldown resistor for EN_GATE100kRINH_XInternal pulldown resistor for high-side PWMs (INH_A, INH_B, and INH_C)EN_GATE high100kRINH_XInternal pulldown resistor for low-side PWMs (INL_A, INL_B, and IN

53、L_C)EN_GATE high100kRnSCSInternal pulldown resistor for nSCSEN_GATE high100kRSDIInternal pulldown resistor for SDIEN_GATE high100kRDC_CALInternal pulldown resistor for DC_CALEN_GATE high100kRSCLKInternal pulldown resistor for SCLKEN_GATE high100kOUTPUT P: nFAULT AND nOCTWVOLLow output thresholdIO = 2 mA0.4VVOHHigh output thresholdExternal 47 k pullup resistor connected to 3-5.5 V2.4VIOHLeakage Current on Open-D