2009年11月2日 第6-1章_中断系统 双语教学_黄英_《单片机原理及应用》讲义(1)new

1、Chapter 6 Interrupt System and Timer System 主讲教师：黄英6.1 Interrupt system Contents：6.1.1 Introduction of Interrupt Technology16.1.2 Interrupt Sources11. External Interrupts12. Timer Interrupts23. Serial Port Interrupt26.1.3 Interrupt Control21. Timer/Counter Control Register（TCON）22. Serial Port Contr

2、ol Register（SCON）33. Interrupt Enable Register（IE）34. Interrupt Priority Register（IP）45. Interrupt Priority Control Rules46. Interrupt Initialization56.1.4 Interrupt Process51. Interrupt Sample52. Interrupt Query53. Interrupt Response54. Interrupt Request Repeal66.1.5 Flow Chart of Interrupt Service

3、76.1.1 Introduction of Interrupt Technology A effective method to solve resource competition. Lets multitask share one resource: Resource sharing technology. Mainly used in real time control.6.1.2 Interrupt Sources 8051 provides 5 interrupt sources: Two external interruptsTwo timer interruptsOne ser

4、ial port interrupt 5 interrupt vectors are assigned in a fixed location.（1） Serial Port interrupt：0023H002AH（8 bytes） （2）Timer/Counter 1 interrupt： 001BH0022H（8 bytes） （3） External Interrupt 1：0013H001AH（8 bytes） （4）Timer/Counter 0 interrupt： 000BH0012H（8 bytes） （5） External Interrupt 0：0003H000AH（8

5、 bytes） The interrupt causes the CPU to jump to the related location, where it has a no-condition jump instruction（LJMP/AJMP/SJMP）pointed to service routine.1. External Interrupts External Interrupts: /P3.2, /P3.3 （generated from external device） Signal Modes: （1）Low Level active （2）Falling edge act

6、ive2. Timer Interrupts Timer0, Timer1 When counting overflows:A timer interrupt is generated.Timer overflow flag（TF0/TF1）is set by internal hardware circuit.3. Serial Port Interrupt When serial port receives/transmits a group of serial data: A serial port interrupt is generated.Receive Flag / Transm

7、it Flag（RI/TI）is set by internal hardware circuit.6.1.3 Interrupt ControlThere are four interrupt control registers: TCON, SCON, IE, IP. 1. Timer/Counter Control Register（TCON） Cell address: 88H Bit addresses: 8FH88H go back Related Bits: TF0/TF1，IE0/IE1，IT0/IT12. Serial Port Control Register（SCON）C

8、ell address: 98H bit addresses: 9FH98HRelated Bits: TI, RI3. Interrupt Enable Register（IE）Cell address: 0A8H bit addresses: 0AFH0A8H go backReset Value = 000 0000b4. Interrupt Priority Register（IP）Cell address: 0B8H bit addresses: 0BFH0B8HReset Value = 0 0000b5. Interrupt Priority Control Rules（1） I

9、f two requests of different priority levels are received simultaneously: The request of higher priority level is serviced.（2） If requests of the same priority level are received simultaneously: An internal polling sequence as follows determines which request is serviced.（3） A low-priority interrupt

10、can be interrupted by a high-priority interrupt but not by another low-priority interrupt.（4） A high-priority interrupt cannot be interrupted by any other interrupt source.（5） If one interrupt request has been responded, other interrupt services of the same priority level are forbidden.6. Interrupt

11、Initialization（1）External InterruptTo set or clear: Global enable bit（EA / IE.7） External Interrupt 0/1 enable bit（EX0 / IE.0, EX1 / IE.2） Interrupt type control bit（IT0 / TCON.0, IT1 / TCON.2）（2）Other InterruptsTo set or clear: Global enable bit（EA / IE.7） Other Interrupt enable bit（ET0 / IE.1, ET1

12、 / IE.3, ES / IE.4）For example: open external interrupt 0 Using byte-operation: MOV IE, #81H; 81H=1000 0001H Using bit-operation: SETB EA SETB EX06.1.4 Interrupt Process1. Interrupt Sample Only for external interrupt. Sampling operation occurs at S5P2 of every machine cycle. External interrupt flag（

13、IE0, IE1）will be set according to the sampling result.2. Interrupt Query CPU queries the status of each interrupt flag bit in order to check：（1）whether interrupt request occur or not （2）which one occurs. Querying operation occurs at the last S6 of every machine cycle. High priority interrupt is to b

14、e queried firstly. Under the equal interrupt priority level, the priority sequence will be as follows: IE0 TF0 IE1 TF1 RI / TI If interrupt occurs, interrupt response will begin at S1 of the next machine cycle.3. Interrupt ResponseHardware will generate an LCALL instruction to get the appropriate se

15、rvice routine. LCALL addr16：“addr16” contains the entrance address of interrupt service routine. For example: “LCALL 0003H” The hardware-generated LCALL pushes the PC contents onto the stack and reloads the PC with an interrupt vector address that depends on the source of the interrupt being service

16、d, as shown in the following table. Interrupt response will be blocked by any of the following conditions:（1） An interrupt of equal or higher priority level is already in progress.（2） The current cycle is not the final cycle of the instruction execution in process.* It ensures that the instruction i

17、n progress will be completed before vectoring to any service routine.（3） The instruction in progress is RETI or any access instruction to the IE or IP registers.* It ensures that at lease one more instruction will be executed before any interrupt is vectored to. If an active interrupt flag is not be

18、ing serviced because of one of the above conditions and is not still active when the blocking condition is removed, the corresponding interrupt request will be ignored.4. Interrupt Request RepealWhen interrupt request responded, the related flag bit of interrupt request should be cleared in order to

19、 avoid respond the same interrupt request again and again.（1）Repeal the Timer interrupt request Timer 0 overflow flag is TF0（TCON.5） Timer 1 overflow flag is TF1（TCON.7） TCON Timer/Counter Control Register When Timer 0 or 1 register overflows, the TF0 or TF1 will be set by hardware. When processor v

20、ectors to interrupt routine, the TF0 or TF1 will be cleared by hardware.So the interrupt request of Timer will be repealed automatically without user interference. （2）Repeal the external interrupt request the external interrupt 0 overflow flag is IE0（TCON.1） the external interrupt 1 overflow flag is

21、 IE1（TCON.3） When external interrupt 0 or 1 is detected on INT0 or INT1 pin, IE0 or IE1 will be set by hardware. When processor vectors to interrupt routine, the IE0 or IE1 will be cleared by hardware. So the interrupt request flag of external interrupt is repealed automatically without user interfe

22、rence. But for different external interrupt signals, repeal methods are different. A. Under signal mode of falling edge active Pulse signal with falling edge from external interrupt pin just appears instantaneously. the interrupt request single of external interrupt is also repealed automatically. B

23、. Under signal mode of low level active Low level signal from external interrupt pin will hold on, which will let hardware set the interrupt request flag again in the next interrupt sampling period. The external signal should be changed from low level to high level artificially when necessary. So hardware method and software method must be combined to realize the repeal of ext