主板上电过程ppt课件

1、主板上電過程,Willess zhang,1,;.,前言,電腦的開機只需要對著Power鍵輕輕一按即可. 可這一按具體是如何使電腦能開機工作的呢?它的整個過程是怎樣的? 以下分幾個部分做講解,2,;.,Content,開機上電動作圖解 主板的電壓定義 主板的主要開機信號介紹 主板開機上電過程（波形和電路）,3,;.,PWRBTN,Slp-s3(+),Pson#(-),+5v/-5v,+3v,+12v/-12v,+5v,+3v,Power ok,NB_ RESET,Reset,SB,NB,CPU,POWER,SUPER I/O OR AS016,Cpu rst,Intel chipset pow

2、er on sequence,Pwr ok,Power Sequence,4,;.,MB Power Sequence,5,;.,主板基本電壓,主板基本電壓有5個，其他電壓都是由這5個基本電壓轉換而得.,6,;.,主板基本電壓,ACPI的Global States分四個狀態 G0G1G2G3,7,;.,主板基本電壓,狀態電壓種類有3種 1.Main power: S0/S1 2.Dual power:S0/S1/S3 3.Standby power:S0/S1/S3/S4/S5,詳細參考附件：,8,;.,Main Power,Main power的產生由SLP_S3#去控制。 按Power B

3、utton PWRBTN#拉low 通知SIOSIO告知NB NB送出SLP_S3#(此時SLP_S3#為高電平) PSON# 被拉low Power Supply產生Main Power.,9,;.,Power-up (Main Power),CH1:+12V Ch2:+5V Ch3:+3V,Main power (+12V,+5V,+3V) almost ramp up at the same time. The main power ramp behavior depends on the power supply design.,10,;.,Standby Power,1， 在MB上，

4、power supply只提供+5VSB一種standby電壓, 其他standby power都由它轉出來的。 2，Standby power上電(插上power cord)主板就會有，但其提供的電流有限。,11,;.,Dual Power,Dual power由standby power和main power提供，他存在於S0,S1,S3這幾種狀態下，由Gate信號去控制哪一個power輸出。,12,;.,主板信號簡介,RTCRST# RSMRST# PWRBTN# SLP_S3# PS_ON# PWROK PLTRST#,13,;.,RTCRST#,Battery,3.0V,BATT,2

5、.6V,G3 State,BATT comes from BATTERY at G3 state. So BATT will be 2.6V at G3 state. BATT comes from +3VSB at S5 state. So BATT will be 2.9V at S5 state.,S5 State,2.9V,RTCRST#有效:在G3狀態時,拔掉battery,此時SB收到低電平,會清掉COMS 內容;若要給主板維持時間或CMOS內容, RTCRST信號需要是高電平.,14,;.,+3VSB,S5 State,+5VSB,RSMRST,After plugging po

6、wer cord, +5VSB ramps up. +3VSB is regulated from +5VSB. 32ms after +3VSB ramps above VTRIP (2.2V), RSMRST asserts. RSMRST will re-assert after AC power loss, which acts like a wake up event of SB and causes the de-assertion of SLP_S3# to turn on the system.,RSMRST#,Resume reset active表示所有的standby p

7、ower都OK.,RSMRST#: Resume Well Reset, this signal is used for resetting the resume power plane logic.,15,;.,AUXOK Logic Example:,Let VPQ3.1 ramps up slower than +3VSB. It is to meet the spec that RSMRST(AUXOK) needs to ramp up after VTR is ready with a delay (20ms for SB600). To precisely estimate th

8、e resulting delay from +3VSB to AUXOK, we need to implement the RC charge formula.,VC,If VCC=3.3V, assuming 20ms is needed: t=RC=20ms VC(20ms)=2.08V VC(18.63ms)=2V If VCC=5V, assuming 20ms is needed: 2. t=RC=20ms VC(20ms)=3.16V VC(10.22ms)=2V RC is chosen by substituting VC(t), VCC, t and solve for

9、RC.,RSMRST#,16,;.,PWRBTN#,PWRBTN#: Power Button, #:代表低電平有效,17,;.,PWRBTN#,Pin6 and pin8 is connected to the power button on the chassis. Pressing power button generate a low pulse to SB and SIO. Power button can be programmed to generate suspend, hibernate or shut-down event. Generally PWRBTN# of SB

10、is internal pulled high, R1336 is reserved to avoid internal pull-high malfunction. This must be pulled to standby power.,5. CB918 must be installed: 1. Debounce, 2. Prevent ESD from directly going into SB and SIO. 1000PF is a commonly used value. 6. To achieve better ESD resist performance, CB918 s

11、hould be placed near front panel header.,18,;.,SLP_S3#,SLP_S3#: Sleep Control,SLP_S3# is for power plane control. This signal shuts off power to all non-critical systems when in S3(Suspend to RAM),S4(Suspend to Disk), or S5 states.,19,;.,SLP_S3#,PWRBTN#,SLP_S5#,SLP_S3#,PS_ON#,S0 State,Press Power Bu

12、tton,In Intel platform, SLP_S3# is always used to turn on the power supply. When resuming from S3/S4, any wake up event will cause the de-assertion of SLP_S3#SLP_S5#, and the rest of the power-up power sequence is the same with those resuming from S5. Some SIO, ex:SMSC5127, uses inverted SLP_S3# to

13、generate nPS_ON#. In SIS platform, PS_ON# is generated from SB itself (ex:SIS 968).,+12V,+5V,+3V,ATX POWER,SLP_S4#,20,;.,PSON#,PSON# 是低有效信號,當此信號為Low時,Power Supply送出+3.3V,+5V,-5V,+12V,-12V等電壓. 而當此信號被拉High時,Power Supply停止送出上面的電壓. 利用此信號可以設計“ Soft Power down” 的關機功能. 當使用者對作業系統下關機命令時. 作業系統亦可關閉所有的應用程式並利用此腳

14、的功能達到自動關機的動作.,灰色: +5V Power OK signal 綠色: +5V (PS_ON#,電源工作電壓),21,;.,PSON#,在主板上,未開機時(S5時), 此信號PSON#一直被pull up到+5VSB. 當User按下Power Button後,一般由Super I/O將此信號拉low,從而通知Power Supply送電. 當實驗時,可以直接把Power supply的PSON#用導線與GND瞬間導通,則此時Power Supply開始工作.,22,;.,PWROK,PWROK有的資料也叫PWRGD, 是電源準備OK的信號.Power Supply 中會有PWRO

15、K,更多的在主板上,且分很多種, 如CPU_PWRGD, NB_PWRGD, VRMPWRGD, VTT_PWRGD. 當電源送出的+3.3V and +5V達到Normal值的95%時,由Power Supply送出此信號.當+3.3V or +5V 掉到Normal的95%以下時,Power Supply就會把此信號拉Low.當主板收到此信號時,表明電源已經準備ok,可以開始動作. 但是大部分情況下,我們不會使用此信號來通知主板動作 (主板上此PIN一般空接) .而是使用專門的ASIC來偵測+3.3V and +5V電壓,當電源發出的電壓符合要求時,由ASIC發出PWROK信號通知主板動作

16、.,PS. ASIC:Application Specific Integrated Circuit,是专用集成电路.目前,在集成 电路界ASIC被认为是一种为专门目的而设计的集成电路,23,;.,PWROK,The PWRGD_3V is a function of PWRGD_PS, nSLP_S3. The 1-0 transition of nSLP_S3 will cause an immediate 1-0 transition of PWRGD_3V. The 0-1 transition of PWRGD_PS will cause a 0-1 transition of PW

17、RGD_3V. The PWRGD_3V is either immediate of after a 100ms to 120ms delay from the 0-1 transition of PWRGD_PS.,+12V,+5V,3.3V,S0 State,PS_ON#,PWRGOOD_PS,400ms,PWRGD_3V,12V,5V,3.3V,24,;.,PLTRST#,PLTTST信號是對所有main Power信號的reset進行時序控制.,25,;.,上電原理,Power-up Sequence G3 State G3-S5 S5-S0 S3-S0 Power-Down Seq

18、uence S0-S5 S0-G3 (AC Power Loss),26,;.,上電原理,開機上電過程,27,;.,上電原理:,上電過程 上電源由5VSB3VSB,按開關後,SW_ON#對地short被拉低,發到ICH,使SLP_S3#拉高,SIO偵測到此信號後,拉低PS_ON#,同时把PS_ON#送到電源,此時電源發出+/-12v,+/-5v,+3.3v電壓,待穩定輸出90%後,電源發出PWRGD_PS至SIO,SIO再發出PWRGD_3V至南北橋,南橋偵測到此信號後發出H_PWRGD至CPU.此時主板開始工作.,28,;.,電源時序 1. PC電源不僅輸出電壓，還要與主機板有信號聯繫，兩者

19、在時間次序上有一定的關係，這就叫做時序。時序是電源與主機板良好配合的重要條件，也是導致電腦無法正常開關機，以及電源與主機板不相容的最常見原因。 2.時序中最重要的是電源輸出電壓(通常以+5V為代表)與P.G信號，以及PS_ON#信號之間的關係。P.G信號由電源控制，代表電源是否準備好，PS_ON#信號則由主機板控制，表示是否要開機。 3.兩個信號都是通過24芯的主機板電源線來連接的，電腦開關機的工作過程是這樣的：電源在交流線通電後，輸出一個電壓+5VSB到主機板，主機板上的少部分線路開始工作，並等待開機的操作，這叫做待機狀態；,上電原理,29,;.,4.當按下主機開關時，主機板就把PS_ON#信號