FM TransmitterDepartment of Electrical and …

1、fm transmitter fm modulation using vco tmcf ci cdttmctt ft dttmctas fccpm cos vin fout f c- gain of vco c - free running frequency of vco corresponding dc bias 1 block diagram dc bias vcc/2 vco painput chipset 4046 phase-locked loop lm7171 wide-band power amplifier 741 op amp 4046 pll only use the v

2、co 4046 vco characteristic c1=100pf schematic pcb layout considerations the signal traces should be short and wide to lower the impedance. the width of the signal traces has to satisfy current driving capacity. any used board area should be shorted to ground to reduce ac noise. sockets and pads will

3、 induce extra capacitance, so components should be directly soldered to board. surface mount components are preferred over discrete ones for less lead inductance. pcb layout measured results carrier frequency: 15mhz bandwidth: controllable output power: 500mw fm receiver fm demodulation using pll sf

4、kks sfkk vp vp i f evf vk s 1 i pv p e sfkks sfsk v tmcs fi pfdlf vco ve in 2 loop filter design crrn kk vp n 21 nl 4 7.0 2 2 cr n 3 vco design vco free running frequency = carrier frequency vco frequency range is no smaller than bandwidth large vco gain will increase pll natural frequency n and thu

5、s improves pll tracking capability block diagram lnapfdlf vco amp bpf chipset 4046 pll clc425 wide-band lna 4046 pll schematic pcb layout superheterodyne fm receiver block diagram amp input matching mixer if amp + if filter lo fm demodulator chipset tda7000 fm radio lm3875 audio power amplifier tda7

6、000 4 if filter quadrature demodulator crrjr sh 212 1 1 fin vout if harmonic distortion if=70khz khzififififif152 khzrf75 if distortion suppression fll correlator to suppress interstation noise not modulated lightly modulated heavily modulated schematic pcb layout monolithic fsk transmitter 5 block

7、diagram a/d converter shift register pll dual modulus prescaler analog input reference frequency output clockdata sampling rate digital input inverter nand 2 input nand 3 input nand 4 input nor 2 input xor transmission gate edge-triggered d flip-flop d flip-flop with clear voltage comparator 8-to-3

8、encoder a/d converter parallel-serial shift register phase-frequency detector vco dual modulus prescaler 6 output driver to drive capacitive load with minimum delay n in l c c a 1 in l c c nln pn wwa, 0 pn wwa, 1 pn n wwa, 1 capacitor driving capability cl=100p f=50mhz synthesizer synthesizer respon

9、se adc and sr response chip layout digital switching noise 7 noise mechanism digital switching injects current into substrate through various kinds of capacitance, which propagates through the substrate and affects analog circuits. digital switching draws current from power supply rail with impedanc

10、e and thus creates voltage drop on power supply rail. digital switching noise in pll pll is a typical mixed-signal integrated circuit pfdlfvco /n noise coupling simulation results error voltage vco output noise reducing techniques use differential topology separate power supply rails use guard rings

11、 multi-chip module heterogeneous integration test structure 1 pfdlfvco /n all building blocks share power supply rails chip layout 1 test structure 2 pfdlfvco /n the counter uses separate power supply rails chip layout 2 test structure 3 pfdlfvco /n the counter uses separate power supply rails the p

12、fd and vco are shielded and ring guarded guard ring p+p+ p-type substrate sink the coupling on-chip shielding metal 3 icsvia2 via1 contact ohmic contact radiation chip layout 3 test structure 4 pfdlfvco /n the counter uses separate power supply rails use guard rings around pfd and vco implement lc v

13、co lc vco lower phase noise than ring oscillator oscillator basics p r l c 1 vgm 1 v p r- tank loss lc 1 0 p m r g 1 positive feedback of 2n phase shift unity loop gain l r q p 0 phase noise is reverse proportional to q 8 chip layout electromagnetic coupling microstrip line coupling l s w 1 2 34 9 e

14、lectric field distribution even mode odd mode impedance matrix 2 cot 2 cot 2 csc 2 csc 2 cot 2 cot 2 csc 2 csc 2 csc 2 csc 2 cot 2 cot 2 csc 2 csc 2 cot 2 cot l zzj l zzj l zzj l zzj l zzj l zzj l zzj l zzj l zzj l zzj l zzj l zzj l zzj l zzj l zzj l zzj z oooeoooeoooeoooe oooeoooeoooeoooe oooeoooeo

15、ooeoooe oooeoooeoooeoooe - propagation constant 22 c zoe - even mode characteristic impedance zoo - odd mode characteristic impedance different configurations low pass band pass band pass band pass experiment setup ground plane fr-4 substrate metal (copper) line 2 metal (copper) line 1 signal genera

16、tor spectrum analyzer ghzmhzf9.2100 dbmp0 ? ? p f coupling results the coupling depends on l, w, s, and integrated inductor coupling coupling between integrated spiral inductors coupling from spiral inductors to transistors 10 2.5d integrated inductor 11 interference effects on pll performance 12 re

17、ferences 1.jerry d. gibson, principles of digital and analog communications 2.floyd m. gardner, phaselock techniques 3.roland e. best, phase-locked loops theory, design, and applications 4.w.h.a. van dooremolen and m. hufschmidt, a complete fm radio on a chip 5.r. jacob baker, harry w. li, david e.

18、boyce, cmos circuit design, layout, and simulation 6.j. navarro soares and w.a.m. van noije, a 1.6-ghz dual modulus prescaler using the extended true-single-phase-clock cmos circuit technique, ieee journal of sscc, vol.34, no.1, jan 1999 7.patrik larsson, measurements and analysis of pll jitter caused by digital switching noise, ieee journal of sscc, vol.36, no.7, july 2001