借助DDS的精密频率的一种替代方法外文资料翻译毕业论文

1、外文出处:Arthur SchwilchChristoph Goste li附 件：1、外文资料翻译译文；2、外文原文。指导教师评语：该生的外文翻译，紧扣论文的主题，语句较通顺，翻译较 准确，说明前期准备阶段的文献调研做了一定的工作，达到了 预期的目的。签名： 2012 年 4 月 20 日附件1外文资料翻译译文借助DDS的精密频率的一种替代方法频率测量的方法基于闭环组成，主要是一个频率比较器（FC）和直接数字合成 器（DDS）,对此在本文中进行了介绍。DDS作为标准信号发生器在FC的投入之中 扮演一定的角色。FC接受了 DDS的硬限幅波形以及未知的频率。从比较两个信 号的输出，控制逻辑向上/

2、向下计数器产生了。计数器的输出频率设定字（FSVV 代理指示的DDS生一个新的正弦波频率接近未知之一。当循环沉淀，频率设定字给出了未知的高频数字估计。优势是从DDS固有的高分辨率和环路噪声免疫力 而来，从而设计同样精确和不受影响的频率计。 所有额外相关的阶段都被仪器的 显示器显示出来。1简介最常用的测频技术采用计数在预定的时间窗口（光圈）的未知频率的脉冲的计数器。此外，凡任何参考频率的脉冲在一个或多个未知一期计算方法也很常见。 在后一种情况下，代替频率的周期只是估计的。本文献的第1部分的某些文件处理了低频率的测量问题并集中在心脏（心脏）信号的频率范围（几赫兹）或在 电源频率（50-60赫兹）。

3、这些技术实际上是在测量讯号的时间，并使用一些方 法来计算它的倒数，即频率。在第2中，频率由查找表的方法计算。其他4-6 的内容是关于微处理器或以微控制器为基础的。上述方法的特点是开环方法，即数字计数器来计数在预定tinle间隔，之后计算结果。其闭环形式刻画了本文提 出的方法。这个术语“闭环”我们用来记一些反馈排序。一个已知（控制）的频 率波形在电路中产生，并反馈到强制它来接近未知的（输入）的频率的频率比较阶段。产生上述提及的受控的频率波形是一个直接数字合成器。2 直接数字频率合成器一个典型的直接数字频率合成器包含一个正弦波（正弦查找表LUT样品的RAM在限定相位跳跃的频率设置字的控制方式下来搜

4、寻这些样本。一个典型 的频率设置字是32位宽，但48位合成器在较高的频率分辨率也可使用。 一个相位累加器产生连续的正弦查找表的地址，并生成一个数字正弦波输出。DDS的数字部分，即相位累加器和查表，被称为数控振荡器（NCO。最后阶段，这相对于 前一个主要是模拟，包括一个 D/ A转换器在一个过滤器之后。过滤器使数字化 的正弦波更平稳，生产连续输出信号。在凡方波输出需要的应用中，这由一个硬限制器在经过过滤器之后得到。这不等于使用例如蓄电池的，而不是硬过滤和波 形输出最高位有限，因为会遇到很大的抖动。对于n位系统的输出信号的频率是 按以下方式计算的；如果相位步等于1,将累加器的计数加1,以时钟周期，

5、以满 足整个LUT和生成一个周期的输出正弦波。这是该系统能生成的最低的频率，也 是它的频率分辨率。设置FSV为二，计数器的结果间隔数为二，以时钟周期来完 成一个周期的正弦波输出。它可以很容易地表明，对于任意整数m其中m ，所采取的时钟周期数旨在产生一个输出的正弦波周期/米，输出频率（fDDS）和频率分辨率（fres ）给出由下列公式:fDDS=m fclk2nfres= fclk/2n对于n = 32，有一个fclk = 33 MHz 的时钟频率，频率分辨率为 7.68兆赫兹如果n是增加至48个具有相同的时钟频率，分辨率为 120 nHz是可能的。3.被提议的频率测量技术产生我们目前的设计的想

6、法来自 DDS的频率分辨率极高的设备并且由它的 封闭循环的形式抗干扰执行。一个（已知）频率源，即DDS采用于一个闭环并且被迫逐步产生频率等于未知输入输出。一个在DDS系统的经验法则是可以接受 的最大合成频率为时钟频率的25%（远低于奈奎斯特限制）。根据这一点，我们 的原型使用一个33 MHz的时钟将有效地数到8兆赫。在砷化傢产品来看，我们 可以看到，最近的DDS设计可以在高达400兆赫的时钟频率范围运作。因此，目 前的方法，频率计数器工作频率达 100 MHz是可以设计的。该决议将取决于 FSW 的数量和时钟频率。DDS的时钟频率是非常重要的，因为它减小，该方法的决 议（定义为fclk /）更

7、出色，即它变得更精细的改进。时钟频率下降的影响是其最大输出频率，限制计数器的最大计数随之降低。主要模块已被证明。其中包 括：频率比较和DDS为了克服特定频率比较器的一些缺点校正阶段已被纳入 这一阶段也可用于测量提取，以显示正确的读数。3.1电路的操作该电路工作在一个新的测量 DDS的输出频率会在一开始以逐次逼近的方法 控制这样一种方式。最初的DDS频率将有一半为它的最大值。此外， 该步骤将频 率近似等于DDS的最大频率的1/4。根据比较器输出的频率，在每一个近似值 中频率被分成两个并且增加或减少到 DDS的 FSW中。在步长下降到一时逼近过程 停止。在此之后，向上/向下计数器替代逼近机制。在适

8、当的修正和解码后，数 码的FSW被显示在在一个输出设备中，即一台液晶显示器或任何其他合适的方 式。或者，也可以进行数字记录，也可以由计算机阅读。由于这一初步的方法， 我们可以说，被提议的方法是基于被迫产生和未知几乎相等的频率的数字控制合 成器。3.2频率比较频率比较似乎是在设计中最关键的阶段。该实现是基于一种改进的相位/频率比较器，由飞利浦在74HC4046 PLL设备中生产。它主要包括两个二进制计数 器，共计两个和一个RS触发器。频率比较器的功能是基于频率较低，即较大的 时期的原则，包括（拥抱）至少有一个或多个频率较高（小周期）完整周期。这 意味着，两个或两个以上的较高频率上升边缘的波形在较

9、低频率周期内。鉴于上述情况，电路操作如下：当第一个计数器（井1）在一个时期内遇到DDS的两个 未知频率的上升边缘，它设置 RS触发器的输出。RS触发器的逻辑“ 1”在向上/ 向下计数器的U / D的控制输出中起作用，强制 DDS升高输出频率。相反，当第 二个计数器（井2）在一个周期内记录两个未知的频率的上升的 DDS俞出的边缘， 它又恢复成RS触发器的输出的。这个动作降低了 DDS的频率。乍一看人们可以 认为，合成频率可达到实测（鳍），然后计数器停止运作。不幸的是并非如此。一个充满活力的机制代替了。该电路需要一些时间来实现正确的频率的关系。我们将把这个时间称为“迟滞”。迟滞取决于最初的DDS输

10、出时序关系和未知频率。 最初，在滞后期，有关更大的频率的指示是不明确的，即它可以是错误的。当两 个歧义在更高的频率上升边缘波形发生在较低的一个时期。如果我们考虑到案件的DDS的频率等于未知之一，我们会发现，比较器的输出将切换，说明或者是DDS的频率高于或低于下限未知。这实际上是一个可以接受的和预期的条件，因 为（在电压比较器）的平等是不可能存在的迹象。在我们的例子中，这不是一个 问题，因为这个电路是在一个封闭的循环之中。 该循环将采取，经过一段短暂的 时间，迟滞等情况将得到扭转的行动方式。 滞后的时间是可变的。这种情况被控 制，也将在后面解释。虽然模拟执行频率的比较将产生更加强劲的噪音，我们坚

11、持数字实现，原因有三：在超大型积体电路或可编程逻辑器件（PLD实现容易，没有模拟组件，频率范围宽的操作和更短的需要响应时间。3.3频率比较器和数字合成器之间的互动在频率比较器“实现”的未知频率逐次逼近之后，合成的频率较高（低）于未知，并在控制向上/向下计数器的输出端产生计算向下（上）一个逻辑0 （1） 的方向。如前所述，这个计数器的输出被认为是从 FSV到DDS勺阶段。在最初的 DDS频率低时，合成频率将会逐步增加，达到未知之一。这不会通过频率比较器“实现”和合成频率将会在一些时钟周期继续增加， 直到比较器检测出它的两个 输入频率的正确关系，未知的一方和 ddS俞出。在相反（降低）的情况下，同

12、样 的现象也将会被观察到。这是因为前面提到的滞后作用。当DDS输出（fDDS已接近鳍，由于滞后性，没有特定的频率合成。相反，它摇摆于F1和F2之间，其中F1和F2是频率对称摆动的两个极端值。DDS的输出可以被看作是一个三角波形的频率调制的载体。三角波形是FSW施加到DDS的模拟表示法。较低的形迹 显示一个比较典型的频率输出。在相同的图上， 上部的描绘，以模拟的形式显示 的FSW勺变化，这是因为它企图接近正确的值。利用辅助硬件电路这个波形已被 俘获：数字至模拟转换器（DAC连接到U / D转换计数器（最高位），以研究操 作的输出。这款DAC不会显示在电路的框图中。下跟踪的 U / D命令（输入）

13、到 计数器上，而跟踪是一个假设的“调频”波形被不同的规定。很明显，使用“假 设”是因为没有一个可用的波形在电路（除辅助DAC中。相反，其相等数值存在。三角波形的坡度大小对于常数输入频率是恒定并且取决于U/ D转换计数器（水平轴）时钟和DAC（垂直轴）的电压基准。这里的坡度为 k ? fin。3.4原型硬件的描述用于评估的目的，两个原型在实验室已建成。第一种方法是一个低频率的工具（工作达15千赫）。这次实施的目的是研究该原则的操作方法。接下来，一个 更高的频率原型制造出来了，在此进行更详细的描述。为了使原型的数字部分（频 率比较，连续计数器，校正阶段）生效，两个产自Altera （EPF8064

14、LC68 - 12）的PLD器件被使用了。这些设备和由高通 Q2240I - 3S1所生产DDS相互联系。 DDS具有32位输入和一个12位输出的正弦查找表（LUT。该12位输出的LUT 送入到由模拟设备AD9713B发出的D / A转换器中。其模拟输出连接到I / V放 大器（电流电压转换器）。由于DAC工作，生成的正弦波具有较高的谐波。这些 谐波在DAC之后将从过滤器删除。这次调整阶段一部分实施在PLD一部分在微控 制器。基于频率比较器的上下命令，我们存储两个极端值，FSW1和FSW2然后再进入微控制器Atmel AT89C52转换成数字表示并反馈到LCD显示器。该微控 制器还控制着整个运

15、作的原型。仪器的行为和预期的一样，和常规的频率计数器 工作台是一样的。在数字示波器的帮助下， 测量采用较低速度跟踪检查。每个状 态，波形的高或低，相当于一个测量所需的时间。4结论在该文件中频率测量的替代方法已经提出。已经被指明，在大多数情况下， 对于相同频率的解决方案，这种方法比传统方法更快。另一方面，由于DDS的固有高频率的特点，该方法的精度非常高。这种可作为振荡器的合成器，在未知的 输入频率范围被驱使“振荡”。与常规方法的比较已经给出，两个原型已建成并 在实验室测试。这种方法的第二个主要优点是，如果重复频率测量，工具一直锁定，频率测量不重新从头开始，而是自动驱使到更低或更高的值。换句话说，

16、循 环有能力按照输入信号频率的变化而改变。在传统的计算技术里，计算过程为每 个新的测量而重复（重新启动）。另一个重要优势是该系统的抗噪声能力，由于 其闭环的性质。一个详细的噪音行为的研究已经在本文中指出。这主要是因为本文的目的是要提出一个频率测量的替代原理。此外，该系统的最终输出采取了一些进一步的（测量校正）有助于抗噪声能力的后处理 。附件2:外文原文An alternative method of precise frequency by the aid of a DDS ContentsA method of freque ncy measureme nt based on a close

17、d loop composed mainly of a Frequency Comparator (FC) and a Direct Digital Synthesizer (DDS) is presented in this paper. The DDS serves as refere nce sin ewave sig nal gen erator act ing at one of the FCs in puts. The FC accepts the hard-limited waveform of the DDS as well as the unknown frequency.

18、From the comparison of the two signals a logic output that controls an up/down counter is produced. The counters output acting as the Freque ncy Sett ing Word (FSW) in structs the DDS to produce a new sin ewave closer in frequency to the unknown one. When the loop settles, the FSW gives the digital

19、estimate of the unknown freque ncy. Adva ntage is take n from the in here nt high resolution of the DDS and noise immunity of the loop, to design an equally precise and immune frequency meter. All the additional associated stages up to the in strume nts display are prese nted.1 IntroductionThe most

20、com monly used freque ncy measureme nt tech nique adopts coun ters that count the pulses of the unknown frequency during a predefined time window (aperture). Apart from this, tech niq ues where the pulses of a refere nce freque ncy are coun ted duri ng one or more periods of the unknown one are also

21、 com mon. In the latter case, the period in stead of the freque ncy is estimated .Some papers in 1 in the literature deal with the problem of low frequency measurement and are focusing in the frequency range of cardiac (heart) signals (a few hertz) or in the mains frequency (50-60 Hz). These techniq

22、ues are actually measuring the period of the signals and use some way to calculate its reciprocal, the freque ncy. In 2, the freque ncy is calculated by the method of look-up tables. Others 4-6 are microprocessor or microc on trollerbased.The above methods can be characterized as open-loop methods i

23、.e. digital counters are used to count during a predefined tinle interval and calculate the result afterwards. Its closed-loop form characterizes the proposed method in this paper. By the term closed-loop we denote some sort of feedback. A waveform with a known (con trolled) freque ncy is produced w

24、ithi n the circuit and is fed back to the freque ncy comparis on stage which con secutively forces it to approximate the unknown (in put) freque ncy. The device that produces the above men ti oned waveform of con trolled frequency is a Direct Digital Synthesizer.2 Direct Digital SynthesisA typical D

25、irect Digital Syn thesizer con sists of a RAM containing samples of a sin ewave (si ne look-up table, LUT). These samples are swept in a con trolled manner by the aid of a Frequency Setting Word (FSW), which determines the phase step. A typical FSW is 32-bit wide, but 48-bit synthesizers leading in

26、higher frequency resoluti on are also available. A phase accumulator produces the successive addresses of the sine look-up table and gen erates a digitized sine wave output. The digital part of the DDS, the phase accumulator and the LUT, is called Numerically Con trolled Oscillator (NCO). The final

27、stage, which in contrast to the previous one is mostly analog, consists of a D/A converter followed by a filter. The filter smoothes the digitized sin ewave, produci ng a con ti nu ous output sig nal. I n the applicati ons where a square wave output is needed, this is obtained by a hard limiter afte

28、r the filter. It is not equivale nt to use e.g. the MSB of the accumulators output in stead of the filtered and hard limited waveform because sig nifica nt jitter will be encoun tered.The frequency of the output signal for an n-bit system is calculated in the follow ing way; If the phase step is equ

29、al to one, the accumulator will count by on es, taking 2n clock cycles to addressthe entire LUT and to generateone cycle of the output sin ewave. This is the lowest freque ncy that the system can gen erate and is also its frequency resolution. Setting the FSW equal to two, results in the accumulator

30、counting by twos, taking 2n J clock cycles to complete one cycle of the output sin ewave. It can easily be show n that for any in teger m, wherem2, the nu mber ofclock cycles take n to gen erate one cycle of the output sine wave is 2n/m, and theoutput frequency (fDDS)and the frequency resolution (fr

31、es) are given by thefollowing formulas :m fclkfDDS=:2nfres= fclk/ 2nFor n = 32 and having a clock frequency of fclk = 33 MHz, the frequency resolutio n is 7.68 mHz. If n is in creased to 48, with the same clock freque ncy, a resolutio n of 120 nHz is possible.3 The proposed frequency measurement tec

32、hniqueThe idea that led to our prese nt desig n came from the extremely high freque ncy resolution of the DDS devices and is enforced by the noise immunity of its closed loop form. A (known) frequency source, the DDS, is employed in a closed loop and is forced progressively to produce an output with

33、 a frequency equal to the unknown in put . A rule of thumb in the DDS systems is that the maximum acceptable syn thesized freque ncy is about 25% of the clock freque ncy (well below the Nyquist limit). Accord ing to this, our prototype that uses a 33 MHz clock would effectively count up to 8 MHz. Lo

34、oking at the GaAs products, we can see that recently available DDS devises can operate at clock freque ncies up to the exte nt of 400 MHz. Therefore, by the prese nt method, freque ncy coun ters work ing up to 100 MHz can be desig ned. The resolutio n will depe nd on the nu mber of FSW bits and the

35、clock freque ncy. The clock frequency fclk of the DDS is very critical because as it decreases, the resolution of the proposed method (defined as fclk/ 2n) becomes finer i.e. it improves. The impact of the clock frequency decreaseis the subsequentdecreaseof its maximum output frequency that limits t

36、he counters maximum count. The major blocks have bee n show n . Among them are the Freque ncy Comparator and the DDS. To overcome some disadva ntages of the specific freque ncy comparator a correct ion stage has bee n in corporated. This stage is also used for the measureme nt extract ion in order t

37、o display the correct read ing.3.1 Operation of the circuitThe circuit operates in such a way that at the begi nning of a new measureme nt the DDS output freque ncy would be con trolled in a successiveapproximati on way. The initial DDS frequency would be half of its maximum. In addition, the freque

38、ncy step of the approximation would equal the 1/4 of the DDS maximum frequency. On every approximatio n the freque ncy step is divided by two and added or subtracted to the FSW of the DDS, depe nding on the output of the Freque ncy Comparator. The approximation procedure stops when the step size dec

39、reasesto one. After that, an up/dow n coun ter substitutes the approximati on mecha ni sm.The digital FSW, after the appropriate correct ion and decod in g, is prese nted in an output device i.e. an LCD display or any other suitable means. Alter natively, it can be digitally recorded or it can be re

40、ad by a computer.As con clusi on of this in itial approach we could say that the proposed method is based on a Digital Con trolled Syn thesizer which is forced to produce a freque ncy almost equal to the unknown one.3.2 Frequency comparisonThe freque ncy comparator seems to be the most critical stag

41、e of the desig n. The implementation is based on a modified phase/frequency comparator proposed by Philips in the 74HC4046 PLL device. It con sists primarily of two binary coun ters, counting up to two and an RS flip-flop.The function of the frequency comparator is based on the principle that the lo

42、wer freque ncy, i.e. larger period, in cludes (embraces) at least one or more full periods of the higher freque ncy (smaller period). This means that two or more rising edges of the higher frequency waveform are included within the lower frequency period. Considering the above, the circuit operates

43、as follows: When the first counter (# 1) encoun ters two rising edges of the unknown freque ncy in one period of the DDS, it sets the output of the RS flip-flop. The logic 1 of the RS flip-flop acting at the U/D con trol in put of the Up/Dow n coun ter forces the DDS to rise its output freque ncy. O

44、n the con trary, whe n the sec ond coun ter (#2) counts two rising edges of the DDS output within a period of the unknown frequency it resets the RS flip-flops output. This action decreases the freque ncy of the DDS.At a first gla nee one could thi nk that the syn thesized freque ncy could reach the

45、 measured one (fin) and then the operation of the counter stops. Unfortunately this is not the case. A dyn amic mecha nism takes place in stead. The circuit n eeds some time to realize the correct frequency relation. We will refer to this time as hysteresis. Hysteresis depends on the initial timing

46、relation of the DDS output and on the unknown frequency. Initially, during the hysteresis period, the indication regarding the larger frequency is ambiguous i.e. it can be erroneous. The ambiguity settles when two rising edges of the higher freque ncy waveform occur duri ng one period of the lower o

47、n e. If we con sider the case of the DDS freque ncy to be equal to the unknown one, we will find that the comparators output will toggle, in dicati ng alter natively that the DDS frequency is higher or lower than the unknown. This is actually an acceptable and expected con diti on, because (as in a

48、voltage comparator) an equality indication could not exist. In our case this is not a problem becausethe circuit is embedded in a closed loop. The loop will act in a manner that after some short time, the hysteresis, the situati on will be reversed and so on. The durati on of hysteresis is variable.

49、 This situati on is con trolled, as will be expla ined later. Although an an alog implementation of the frequency comparator would look more robust to noise we insisted to the digital implementation for three reasons: ease of implementation in VLSI or Programmable Logic Devices (PLDs) with no n eed

50、of an alog comp onen ts, wide freque ncy range of operati on and shorter resp onse time.3.3 Interaction between frequency comparator and digital synthesizerAfter the successive approximation of the unknown frequency the Frequency Comparator realizes that the synthesized frequency is higher (lower) t

51、han the unknown one and produces a logic 0 (1) at the output which comma nds the up/dow n coun ter to count in the dow n (up) directi on. As previously men ti on ed, the output of this counter is considered to be the FSW to the DDS stage. In the case when the DDS freque ncy was in itially lower, the

52、 syn thesized freque ncy will in crease progressively to reach the unknown one. This will not be realized by the freque ncy comparator and the synthesized frequency will keep on increasing for some clock cycles, until the comparator detects the correct relati on of its two in put freque ncies, the u

53、nknown one and the DDS output. The same phenomenon will be observed for the opposite (decreasing) case also. This is due to hysteresis that was mentioned earlier.When DDS output (fDDS) has approached fin, due to hysteresis, no specific freque ncy is syn thesized. In stead, it swings betwee n f1 and

54、f2, where and f2 are the two extreme values of the freque ncy swi ng lyi ng symmetrically around fin. The DDS output can be con sidered as a freque ncy modulated carrier by a tria ngular waveform. The triangular waveform is the analog representation of the FSW applied to the DDS. lower trace shows a

55、 typical output of the Freque ncy Comparator. I n the same figure, upper trace, is shown in analog form the FSW variation as it is trying to approach the correct value. This waveform has bee n captured using an auxiliary hardware circuit: A digital-to-analog converter (DAC) was connected to the outp

56、ut of the U/D counter (MSBs) in order to study the operation. This DAC is not shown in the block diagram of the circuit. Stated differe ntly, the lower trace is the U/D comma nd (in put) to the coun ter while the upper trace is a hypothetical freque ncy modulati ng waveform. It is obvious that the t

57、erm hypothetical is used because there is not such a waveform available somewhere in the circuit (except for the auxiliary DAC). In stead, its nu merical equivale nt exists. The magn itude of the slope of the eleme nts of the trian gular waveform is con sta nt for con sta nt in put freque ncy and de

58、pe nds on the clock of the U/D coun ter (horiz on tal axis) and the voltage refere nee of the DAC (vertical axis). This slope is 士 k ? fin.3.4 Description of the prototype hardwareFor evaluation purposes two prototypes have been built and tested in the laboratory. The first approach was a low freque

59、ncy instrument (operating up to 15 KHz). The purpose of this implementation was to study the principles of operation of the proposed method. Next, a higher frequency prototype was built which will be described in more detail here .In order to impleme nt the digital part of the prototype, (Frequency Comparator, Successive Counter