多功能数字钟课程设计VHDL代码书上程序改解析

1、library ieee;use ieee.std_logic_1164.all;en tity clock isport(clk1hz:in stdogic;-1hz 脉冲-clk100:in stdogic;-100hz 脉冲-weekclk:in stdogic;-星期调整脉冲-start_stop:in std_logic;-秒表启动 /停止控制-reset:in stdogic;-秒表复位-adclk:in stdogic;-校时脉冲-setselect:in stdogic;-调整位选择脉冲-mode:in stdogic;-功能选择脉冲-showdate:in stdogic;-

2、日期显示-dis:out stdogic_vector(23 downto 0;-显示输出-glisten:out std_logic_vector(5 down to 0;-闪烁指示-weekout:out stdo gic_vector(3 dow nto 0;-星期输出-qh:out std_logic-整点报时-end clock;architecture arch of clock iscomp onent adjustport (adclk: in std_logic;datan: out stdo gic_vector(7 dow nto 0Jend comp onent;com

3、p onent con trolport (setclk: in std_logic;setlap: out std_logic_vector (1 dow nto 0;mode: in std_logic;module: out stdo gic_vector (2 dow nto 0Jend comp onent;comp onent weekco un terport (clk: in std_logic;clk2: in std_logic;q: out std_logic_vector(3 dow nto 0end comp onent;comp onent stopwatchpor

4、t (clk: in std_logic;reset: in std_logic;start_stop: in stdo gic;cen tsec: out stdo gic_vector(7 dow nto 0; sec: out stdo gic_vector(7 dow nto 0;mi n: out stdo gic_vector(7 dow nto 0Jend comp onent;comp onent h_m_s_co untport (clk: in std_logic;set: in std_logic;setlap: in std_logic_vector (1 dow nt

5、o 0;d:i n stdo gic_vector(7 dow nto 0;sec:out stdo gic_vector(7 dow nto 0; min :out stdo gic_vector(7 dow nto 0; hour:out stdo gic_vector(7 dow nto 0; qh:out std_logic;qc: out std_logicJend comp onent;comp onent y_m_d_co untport (clk: in std_logic;set: in std_logic;setlap: in stdo gic_vector(1 dow n

6、to 0; data_i n: in stdo gic_vector(7 dow nto 0; day: out stdo gic_vector (7 dow nto 0; mon th: out std_logic_vector (7 dow nto 0; year: out std_logic_vector (7 dow nto 0Jend comp onent;comp onent displayport (module: in stdo gic_vector (2 dow nto 0;showdate:i n std_logic;clk:in std_logic;setlap:i n

7、stdo gic_vector(1 dow nto 0;watch: in stdo gic_vector (23 dow nto 0;time:in stdo gic_vector(23 dow nto 0;date:in stdo gic_vector(23 dow nto 0;dis: out std_logic_vector (23 dow nto 0;gliste n:out stdo gic_vector(5 dow nto 0 ;end comp onent;sig naldata_i n, mce ntsec,msec,mmi n,ssec,smi n,shour,sdate,

8、sm on th,syear:stdo gic_vector(7 dow nto 0;sig nal setlap:stdo gic_vector(1 dow nto 0;sig nal module:stdo gic_vector(2 dow nto 0;sig nal qc:std_logic;signal watch,time,date:stdogic_vector(23 downto 0;begi nu1:adjust port map(adclk,data_i n;u2:con trol port map(setselect,setlap,mode,module;u3:stopwat

9、ch port map(clk100,reset,start_stop,mce ntsec,msec,mmi n; u4:h_m_s_co unt port map(clk1hz,module(1,setlap,data_i n, ssec,sm in, shour,qh,qc;u5:y_m_d_co unt port map(qc,module(2,setlap,data_i n,sdate,sm on th,syear; u6:display port map(module,showdate,clk1hz,setlap,watch,time,date,dis,gliste n; u7:we

10、ekco un ter port map(qc,weekclk,weekout;watch=mmin&msec&mce ntsec;time=shour&sm in&ssec;date=syear&sm onth&sdate;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;use ieee.std_logic_arith.all;en tity adjust isport (adclk: in stdo gicdata_i n: out stdo gic_vector(7

11、dow nto 0end adjust;architecture arch of adjust issig nal temp2,temp1:std_logic_vector(3 dow nto 0;begi nprocess(adclkbegi nif risin g_edge(adclkthe nif temp仁1001 thentemp2=temp2+1;temp1=0000;elsetemp1=temp1+1;end if;if temp2=1001 and temp仁1001 thentemp1=0000;temp2=0000;end if;end if;data_i n=temp2&

12、temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity con trol isport (setclk: in stdogic;-调整脉冲-setlap: out stdogic_vector (1 downto 0;-调整位选择脉冲 -mode: in stdogic;-功能选择脉冲-module: out stdogic_vector (2 downto 0-功能输出-end con trol;architecture arc

13、h of con trol issig nal ssetlap:stdo gic_vector(1 dow nto 0;sig nal s:stdo gic_vector(3 dow nto 0;begi nprocess(mode,setclkbegi nif mode=1the nssetlap=00;elsif risin g_edge(setclk the n if ssetl ap=10the n ssetlap=00;elsessetlap=ssetlap+1;end if;end if;end process;setlapsssss=0010;end case;end if;en

14、d process;module=s(3 dow nto 1;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;use ieee.std_logic_arith.all;en tity coun ter60 isport (clk: in stdogic;-计数脉冲-clr: in stdo gic;-复位-q: out stdogic_vector(7 downto 0;-计数值-qc:out stdogic-进位输出-end coun ter60;architecture

15、 arch of coun ter60 isprocess(clr,clkbegi nif clr=1the ntemp1=0000;temp2=0000;elsif risin g_edge(clkthe nif temp仁1001 thentemp2=temp2+1;temp1=0000;elsetemp1=temp1+1;end if;if temp2=0101 and temp仁1001 thentemp1=0000;temp2=0000;qc=1;elseqc=0;end if;end if;qv=temp2&temp1;end process;end arch;library ie

16、ee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;use ieee.std_logic_arith.all;en tity coun ter99 isport (clk: in stdogic;-100vhz 计数脉冲-en: in stdogic;-计数使能-clr: in stdo gic;-复位-q: out stdo gic_vector(7 dow nto 0;-计数值-qc: out std_logic-进位-end coun ter99 ;architecture arch of coun ter9

17、9 isprocess(clr,clkbegi nif clr=1the ntemp1=0000;temp2=0000;elsif risin g_edge(clkthe nif en=1 thenif temp仁1001 thentemp2=temp2+1;temp1=0000;elsetemp1=temp1+1;end if;if temp2=1001 and temp仁1001 thentemp1=0000;temp2=0000;qc=1;elseqc=0;end if;end if;end if;qv=temp2&temp1;end process;end arch;library i

18、eee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;use ieee.std_logic_arith.all;en tity dayco un ter isport (clk: in stdogic;-计数脉冲-set: in stdogic;-调整信号-day_in: in stdogic_vector(7 downto 0;-调整输入-day_out: out stdo gic_vector(7 dow nto 0;-天输出-qc: out stdo gic;-进位-day28: in std_logic;-

19、该位为1表示该月为28天-day29: in std_logic;-该位为1表示该月为29天-day30: in std_logic;-该位为 1 表示该月为 30天-day31: in stdogic-该位为 1 表示该月为31天-end dayco un ter;architecture arch of dayco un ter issig nal temp1,temp2:std_logic_vector(3 dow nto 0; sig nal days:std_logic_vector(7 dow nto 0;begi ndays=00101000 when day28=1else00

20、101001when day29=1else00110000when day30=1else 00110001when day31=1else00000000;process(clk,set,day_i n, daysbegi nif set=1 the ntemp2=day_i n(7 dow nto 4;temp1=day_i n(3 dow nto 0;elsif risin g_edge(clkthe nif temp仁1001 thentemp2=temp2+1;temp1=0000;elsetemp1=temp1+1;end if;if temp2&temp仁days the nt

21、emp2=0000;temp1=0001;qc=1;elseqc=0;end if;end if;end process;day_outday28v=0;day29v=0;day30v=0;day31if (year2=0a nd year仁00or (year2=1a nd year仁10 thenday28=0;day29=1;day30=0;day31=0;elseday28v=1;day29v=0;day30v=0;day31day28v=0;day29v=0;day30v=0;day31day28=0;day29=0;day30=1;day31day28=0;day29=0;day3

22、0=0;day31day28=0;day29=0;day30=1;day31day28=0;day29=0;day30=0;day31day28=0;day29=0;day30=0;day31day28=0;day29=0;day30=1;day31day28=0;day29=0;day30=0;day31day28=0;day29=0;day30=1;day31day28=0;day29=0;day30=0;day31day28v=0;day29v=0;day30v=0;day31=1;end case;end process;end arch;library ieee;en tity di

23、splay isport (module: in stdogic_vector (2 downto 0;-功能选择-showdate:in stdogic;-显示日期-clk:in stdogic;-闪烁脉冲-setlap:in stdogic_vector(1 downto 0;-闪烁位选择-watch: in std_logic_vector (23 downto 0;-秒表计数值输入-time:in std_logic_vector(23 downto 0;-时分秒计数 值输入-date:in std_logic_vector(23 downto 0;-年月日计数值输入-dis: out

24、 stdogic_vector (23 downto 0;-显示输出-glisten:out stdogic_vector(5 downto 0-闪烁输出-Jend display;architecture arch of display isbegi nprocess(module,showdate,watch,time,datebegi nif showdate=1the ndisdisdisdisdisglisten(1 downto 0=clk&clk;gliste n(5 dow nto 2gliste n(3 dow nto 2=clk&clk;gliste n(5 dow nto

25、 4=00;glisten(1 downto 0glisten(5 downto 4=clk&clk;gliste n(3 dow nto 0glisten=000000;else gliste nset1v=1;set2v=0;set3=0;q1set1=0;set2=1;set3=0;q2set1=0;set2=0;set3=1;q3set1=0;set2=0;set3=0;end case;elseset1=0;set2v=0;set3=0;end if;end process;library ieee;use ieee.std_logic_1164.all;en tity h_m_s_

26、c ount isport (clk: in std_logic;-1hz 脉冲-set: in stdogic;-调整信号-setlap: in stdogic_vector (1 downto 0;-调整位选择-d:in stdogic_vector(7 down to 0;-调整输入-sec:out stdogic_vector(7 downto 0;-秒输出-min:out stdogic_vector(7 downto 0;-分输出-hour:out stdogic_vector(7 downto 0;-小、时输出-qh:out std_logic;-整点报时-qc: out std

27、_logic-进位-end h_m_s_c ount;architecture arch of h_m_s_co unt iscomp onent sec_m incoun terport (clk: in std_logic;set: in stdo gicd:i n stdo gic_vector(7 dow nto 0;q:out stdo gic_vector(7 dow nto 0; qc:out stdo gicJend comp onent;comp onent hourco un terport (clk: in std_logic;set:in std_logic;d:i n

28、 stdo gic_vector(7 dow nto 0;q: out stdo gic_vector(7 dow nto 0;qc:out stdo gicJend comp onent;comp onent dmuxport (set:in std_logic;setlap: in stdo gic_vector (1 dow nto 0;d: in stdo gic_vector(7 dow nto 0;set1:out std_logic;set2:out stdo gic;q1: out stdo gic_vector(7 dow nto 0;q2: out stdo gic_vec

29、tor(7 dow nto 0;q3: out stdo gic_vector(7 dow nto 0end comp onent;sig nal secset,m in set,hourset: std_logic;sig nal seci n,minin ,houri n:stdo gic_vector(7 dow nto 0;sig nal qcsec,qcm in, qchour: std_logic;begi nu1:dmux port map(set,setlap,d,secset,m in set,hourset,seci n,minin ,houri n; u2:sec_m i

30、ncoun ter port map(clk,secset,seci n, sec,qcsec;u3:sec_m incoun ter port map(qcsec,mi nset,mi nin,min ,qcmi n;u4:hourco un ter port map(qcm in ,hourset,houri n,hour,qchour;qh=qcmi n;qc=qchour;end arch;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_ un sig ned.all;en tity

31、 hourco un ter isport (clk: in stdogic;-计数脉冲-set:in stdogic;-调整信号-d:in stdogic_vector(7 downto 0;-调整时间-q: out stdogic_vector(7 downto 0;-小、时输出-qc:out stdogic-进位-end hourco un ter;architecture arch of hourco un ter issig nal temp1,temp2:std_logic_vector(3 dow nto 0; beg inprocess(clk,setbegi nif set=

32、1the ntemp2=d(7 dow nto 4;temp1=d(3 dow nto 0;elsif risin g_edge(clk the nif temp仁1001 thentemp2=temp2+1;temp1=0000;elsetemp1=temp1+1;end if;if temp2=0010 and temp仁0100 thentemp1=0000;temp2=0000;qc=1;elseqc=0;end if;end if;end process; qv=temp2&temp1;end arch;use ieee.std_logic_ un sig ned.all;use i

33、eee.std_logic_arith.all;en tity mon thco un ter isclk: in stdogic;-计数脉冲-set: in stdogic;-调整信号-monthn: in stdogic_vector(7 downto 0;-调整输入-month_out: outstdo gic_vector(7 dow nto 0;-月输出-qc: out stdo gic-进位-end mon thco un ter;architecture arch of mon thco un ter issig nal temp1,temp2:std_logic_vector(

34、3 dow nto 0;begi nprocess(clk,set,m onthnbegi nif set=1 the ntemp2=monthn(7 dow nto 4;temp1=monthn(3 dow nto 0;elsif risin g_edge(clk the nif temp仁1001 thentemp2=temp2+1;temp1=0000;elsetemp1=temp1+1;end if;if temp2=0001and temp仁0010 thentemp2=0000;temp1=0001;qc=1;elseqc=0;end if;end if;end process;m

35、on th_out=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_ un sig ned.all;en tity sec_m incoun ter isport (clk: in stdogic;-计数脉冲-set:in stdogic;-调整信号-d:in stdogic_vector(7 downto 0;-调整时间输入- q:out std_logic_vector(7 downto 0;-分和秒输出- qc:out

36、 stdo gic-进位-Jend sec_m incoun ter;architecture arch of sec_m incoun ter issig nal temp1,temp2:std_logic_vector(3 dow nto 0;begi nprocess(clk,setbegi nif set=1the ntemp2=d(7 dow nto 4;temp1=d(3 dow nto 0;elsif risin g_edge(clk the nlibrary ieee;use ieee.std_logic_1164.all;if temp仁1001 thentemp2=temp

37、2+1;temp1=0000;elsetemp1=temp1+1;end if;if temp2=0101 and temp仁1001 thentemp1=0000;temp2=0000;qc=1;elseqc=0;end if;end if;end process ; qv=temp2&temp1;end arch;en tity stopwatch isport (elk: in std_logic;-100hz 脉冲-reset: in stdo gic;-复位-start_stop: in stdo gic;-启动 / 停止-centsec: out std_logic_vector(

38、7 downto 0;-百分秒输出，当超过 60分转为秒-sec:out std_logic_vector(7 downto 0;-秒输出，当超过 60 分转为分-min: out std_logic_vector(7 downto 0-分输出，当超过 60 分转为小时-end stopwatch;architecture arch of stopwatch iscomp onent coun ter99port (clk: in std_logic;en: in std_logic;clr: in std_logic;q: out stdo gic_vector(7 dow nto 0;qc

39、: out std_logicend comp onent;comp onent coun ter60port (clk: in std_logic;clr: in std_logic;q: out stdo gic_vector(7 dow nto 0;qc: out std_logicJend comp onent;sig nal qc1,qc2,qc3,qc4,flag:std_logic;signal tcentsec,tsec,tmin,thour:stdogic_vector(7 downto 0; beginu1:co un ter99 port map(clk,start_st

40、op,reset,tce ntsec,qc1;u2:co un ter60 port map(qc1,reset,tsec,qc2;u3:co un ter60 port map(qc2,reset,tm in, qc3;u4:co un ter60 port map(qc3,reset,thour,qc4;process(qc3begi nif risin g_edge(qc3the nflag=1;end if;if flag=1 the n cen tsec=tsec; sec=tm in; min=thour; elsecen tsec=tce ntsec;sec=tsec;min =

41、tmi n;end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;use ieee.std_logic_arith.all;en tity weekco un ter isport (elk: in stdogic;-天脉冲-clk2: in stdogic;-外部星期调整脉冲-q: out stdogic_vector(3 downto 0-星期输出-;end weekeounter; architecture arch of weekeo

42、 un ter is sig nal temp:stdo gic_vector(3 dow nto 0; sig nal cp:stdo gic; beg in cp=clk or clk2; process beg in wait un til risin g_edge(cp; if temp=0111 the n temp=0001; else tempv=temp+1; end if; qv=temp; end process; end arch; library ieee; use ieee.stdo gic_1164.all; en tity y_m_d_co unt is port

43、 ( clk: in stdo gic;-计数脉 冲-set: in std_logic;-调整信号-setlap: in std_logic_vector(1 downto 0;-调整位选择- data_in: in stdogic_vector(7 downto 0;-调整输入-day: out stdogic_vector (7 downto 0;-日输出-month: out stdogic_vector (7 downto 0;-月输出-year: out stdogic_vector (7 downto 0-年输出-;end y_m_d_count; architecture ar

44、ch of y_m_d_count is comp onent dayco un ter port ( clk: in std_logic; set: in std_logic; day_i n: in stdo gic_vector(7 dow nto 0; day_out: out stdo gic_vector(7 dow nto 0; qc: out std_logic; day28: in std_logic; day29: in std_logic;day30: in std_logic; day31: in std_logic ; end comp onent; comp one

45、nt mon thco un ter port ( clk: in stdo gic; set: in std_logic; monthn: in stdo gic_vector(7 dow nto 0; mon th_out: out std_logic_vector(7 dow nto 0; qc: out std_logic ; end comp onent; comp onent yearco un ter port ( clk: in std_logic; set: in std_logic; year_i n: in stdo gic_vector(7 dow nto 0; yea

46、r_out: out stdo gic_vector(7 dow nto 0 ; end comp onent; comp onent dmux port ( set: in std_logic; setlap: in std_logic_vector (1 dow nto 0; d: in stdo gic_vector(7 dow nto 0; set1:out std_logic; set2:out stdo gic; set3:out std_logic; q1: out stdo gic_vector(7 dow nto 0; q2: out stdo gic_vector(7 dow nto 0; q3: out stdo gic_vector(7 dow nto 0 ; end comp onent; comp onent days_c on trol port ( mon th: in stdo gic_vector(7 dow