S32K 培训资料 单片机介绍

1、Confidential and Proprietary TM Carl Culshaw, Systems Engineering, Automotive MCU ARM Cortex in Automotive Architecture & Peripherals KFA family, rev A O c t 2 4 . 2 0 1 4 TM Confidential and Proprietary1 Agenda KFA series KFA family architecture Safety Performance Clocking Power Management ADC & tr

2、iggering subsystem Compatibility Communication peripherals FlexIO Software and Enablement Summary TM Confidential and Proprietary2 KFA Series - Introduction Key Hardware Features High performance ARM Cortex architecture Low power 30% better than todays benchmark Scalability from 16KB to 2MB embedded

3、 flash FlexCAN with CAN FD option FlexIO for configurable number of LIN, SPI, I2C Targeting ASIL-B applications Security Key Software Features KDS (Kinetis Design Studio) Autosar MCAL and OS Non-autosar Low-Level Drivers Model-based design support Extensive 3rd party offering TM Confidential and Pro

4、prietary3 General Purpose MCU Roadmap 2014 2015 2016 2017 Entry 90nm First Sample Date (left edge) Product Qualification (right edge) Proposal Planning Production or Execution 180nm Last Updated 10SEP14 2018 KFA 512 M4 up to 120MHz KEA64 M0+ 40MHz KEA8 M0+ 48MHz Mainstream High performance KEA128 M0

5、+ 48MHz 64-128kB, LIN, CAN, 64-80pin 16-64kB, LIN, 32-64pin 8kB, LIN, 16-24pin 256-512kB, FlexIO, CAN-FD, 48-144pin 64-128kB, LIN, CAN, 32-64pin KFA 1M M4 up to 150MHz 768kB-1M, FlexIO, CAN-FD, 100-176pin KFA 2M M4/M0+ up to 180MHz 1.5M-2M, FlexIO, CAN-FD, Ethernet, Security 100-176pin KGA 128 M0+ 6

6、4MHz 16-32kB, LIN, 20-48pin KGA 32 M0+ 48MHz High temp (AEC Grade 0) Cortex M4/M0+ TM Confidential and Proprietary4 KFA512 Block Diagram Preliminary and subject to change Communications I/O System Peripheral Bus SWD JTAG Debugger Debug RAM Up to 64KB System Peripheral Bridge Flash Up To 512K NVIC Co

7、rtex M4 80/120MHz FPU, DSP, MPU EEPROM 4KB 2x16ch, 12bit Dual ADC 2 ACMP Flex IO peripheral 16ch / 64ch eDMA WDT EWM PMC 2.7 - 5.5V POR FLL Clk Mult LVD Ext Osc (4 - 40MHz) Int R/C OSC (48MHz 1%) Int LP Osc (128KHz) SCG High performance ARM Cortex M4 up to 120MHz w FPU eDMA from Qorivva family Softw

8、are Friendly Architecture High RAM to Flash ratio Independent CPU and periph clocking 48MHz IRC no PLL init required in LP registers maintained in all modes Programmable triggers for ADC no sw delay counters or extra interrupts Functional safety ISO26262 support for ASIL B or higher MPU ECC on Flash

9、/Dataflash and RAM Independent internal OSC for Watchdog Diversity between ADC and ACMP Diversity between SPI/SCI and FlexIO Core self test libraries Scalable LVD protection Low power Low leakage technology Multiple VLP modes and IRC combos Wake-up on analog thresholds 4x8ch 16-Bit FlexTimer 2 I2C 3

10、 SPI 4 SCI (LIN) 2 PDB 3 FlexCAN w FD 1 PIT Open- Drain IO, KBI, GPIO Digital Components 5V Analogue Components MCU Core and Memories 1 API RTC Operating CharacteristicsI/Os Voltage range: 2.7 to 5.5 V64/100pin compatible within Family Temperature (ambient): -40 to 125COpen-drain for 3.3V and hi-dri

11、ve pins to save BOM Powered ESD protection TM Confidential and Proprietary5 Safety TM Confidential and Proprietary6 MCU HW Know Your Safety System Context How to make the system safe? Optimal partitioning between Safety System HW & SW measures scaled to complexity of vehicle safety function Simple S

12、afety Functions are implemented on a high abstraction level (vehicle & ECU) Complex* Safety Functions are implemented using a combination of low (MCU HW) and high abstraction level (vehicle & ECU) Complex Safety Function (e.g. EPS) Simple Safety Function (e.g. Airbag) EPS, ESP, Engine Management HEV

13、 ASIL D target ASIL A target ASIL B target ASIL C target * A Complex Safety Function (vehicle level) here refers to the combination of a high computational demand for the application combined with a short control cycle. Safety System HW & SW Airbag, Body, DIS RADAR and Vision based ADAS TM Confident

14、ial and Proprietary7 MCU HW The Solution Offering products scaled to vehicle safety function complexity from across the Freescale product portfolio ISO 26262 developed products cover the complete range Standard products cover systems with simple safety functions Where we enable the customer to do th

15、e Qualification, testing and analysis to prove that our component is suitable for the purpose of his safety concept. Covering the whole range efficiently ASIL D target Complex Safety FunctionSimple Safety Function ASIL A target ASIL B target ASIL C target EPS, ESP, Engine Management HEV Safety Syste

16、m HW & SW Airbag, Body, DIS RADAR and Vision based ADAS SafeAssure SEooC HW Developed for ISO 26262 (10.9 Safety Element out of Context) SafeAssure Standard HW Enabled for ISO 26262 (8.13 Qualification of Hardware Components) TM Confidential and Proprietary8 Full ASIL safety tracking KFA family samp

17、le extract TM Confidential and Proprietary9 Single Point Fault Metric RAM ECC Flash ECC Undervoltage monitoring Clock Monitoring Temporal protection Software Watch dog SMPU execution control Register protection CRC Individual Peripheral safety support measures ECC Error Handling Single bits: Flash h

18、andled / repaired automatically Single bits: SRAM Error address capturing Interrupt generated Customer s/w can handle Double bits: Code Flash Machine Exception - software decision If second double bit error - force h/w reset Double bits: Data Flash & SRAM Machine Exception - software decision Custom

19、er s/w can handle Functional SafetyDiversity of safety levels LPSPI or LPSCI v FlexIO Create completely alternate SPI / SCI communication paths Ultra high parallelisation of data integrity Analogue input monitoring Analogue measuring via completely independent system resources Independent references

20、, independent peripherals Class leading monitoring protection schemes TM Confidential and Proprietary10 Safety Support (Cyclic Redundancy Check - CRC) The cyclic redundancy check (CRC) module generates 16/32-bit CRC code for error detection The CRC module provides a programmable polynomial, seed and

21、 other parameters required to implement a 16-bit or 32-bit CRC standard. The 16/32-bit code is calculated for 32 bits of data at a time. CRC Engine CRC Data Polynomial TM Confidential and Proprietary11 Example: Using DMA for CRC Calculation 11 eDMA DMA Request Mux LPUARTs LPSPIs I2Cs FTMs ADCs HSCMP

22、s FlexIO PDB GPIOs 63 DMA Requests SCGSIM clock NVIC error int DMA CH0 int DMA CH1 int DMA CH16 int DMA Mux SPIs DMA Mux CRC Source (Flash) Destination (CRC) TM Confidential and Proprietary12 Safety Support - Watchdog Timer (WDOG) TM Confidential and Proprietary13 Safety Support - External Watchdog

23、Monitor (EWM) TM Confidential and Proprietary14 Performance TM Confidential and Proprietary15 TM Confidential and Proprietary16 KFA512 High Level Architecture TM Confidential and Proprietary17 Operating profile flash reliability The below profile is within the targeted development mission profile fo

24、r qualification and the targeted data retention spec for KFA. Suitable for even the most stringent automotive lighting application. Assume 8000hrs operating (1 year): 2100hrs 125C 3000 105C 1500 40C 1000 25C 400 0C Non-operating (14 years): - 122000hrs 25C average / vehicle stopped TM Confidential a

25、nd Proprietary18 DMA Mux Allocations TM Confidential and Proprietary19 Clocking TM Confidential and Proprietary20 High Level Clocking Architecture TM Confidential and Proprietary21 Clock sources FIRC: 48MHz 60MHz 1% accuracy after trimming, across PVT 300uA consumption SIRC: 8MHz 10% accuracy 20uA c

26、onsumption LPO: 128KHz - RUN - STOP - RUN - VLPS approach Use API to wake up periodically Clock core and ADC0 from 8MHz SIRC Use STOP state during the sensor stabilization period Return to VLPS unless pre-defined conditions exceeded 2ms 10ms 20mA 35mA 20mA Run Current range RUN from RAM 45ms 1ms 10m

27、s 65ms Run from RAM & read sensor 45ms 10ms 10ms Run from RAM & enable sensor 45ms 1ms 10ms 56ms VLPS Current 300mA STOP VLPS TM Confidential and Proprietary33 ADC & Triggering Subsystem TM Confidential and Proprietary34 KFA512 ADC Configuration ADC0, ADC1 (12Bit) Channel configuration 16 Standard I

28、nternal Channels 3 Special Internal Channels Conversion Time = 1us (incl sample) ENOB = 10.5 bits TUE = +/-6bits 700uA 1us conversion ADC1 12Bit 16 channels Bandgap Ana Supply VrefH PMC ADC0 12Bit 16 channels Bandgap Ana Supply VrefH TM Confidential and Proprietary35 ADC Triggering Scheme Overview T

29、he KFA family supports two types of ADC triggering: ADC software trigger ADC hardware trigger Using PDB Using LPIT Using TRGMUX TM Confidential and Proprietary36 ADC Conversion using DMA Configuration SAR ADC HW Trigger Channel Trigger DMA request DMA 0 Buffer (results) Result Conversion complete DM

30、A request DMA 1 DMA link Buffer (channels) DMA interrupt BCR = 0 1. Trigger starts ADC conversion 2. ADC conversion complete flag starts the DMA 0 3. DMA 0 copies the ADC result to buffer and generates a link to DMA1 4. DMA 1 copies next ADC channel ID from buffer to ADC register 5. When BCR is 0 (D

31、MA done flag), DMA interrupt is generated TM Confidential and Proprietary37 ADC Hardware Trigger Method 1: Using PDB PDB is the suggested ADC triggering module. PDB0 is intended to function with ADC0, so as PDB1-ADC1 and PDB2-ADC2. There are dedicated interconnection between the pair of PDB and ADC.

32、 TM Confidential and Proprietary38 ADC Hardware Trigger Method 2: Using LPIT LPIT is another optional ADC triggering module. Different with PDB, LPIT can be used to trigger any of the three ADCs through TRGMUX. But LPIT only supports 4 independent timer channels, which leads to a limitation of only

33、4 pre-triggers for ADC. The 4 LPIT channels can be used to flexibly trigger any ADC. For example: -4 ch to trigger 13 ADCs at same time, each ADC with 4 result registers -4 ch to trigger 2 ADCs independently, each ADC with 2 result registers - . Note: LPIT doesnt support ADC_COCO feedback, it needs

34、software to correctly control the ADC trigger timing setting. Note: Following diagram only shows PDB0-ADC0, its the same with PDB1-ADC1 and PDB2-ADC2. TM Confidential and Proprietary39 ADC Hardware Trigger Method 3: Direct trigger For direct ADC trigger (not using PDB or LPIT), the ADC supports up t

35、o 4 ADHWTn. TRGMUX Logic “0” - VSS Trigger source A SW pre-trig OR 0 0 0 SW pre-trig ADHWT ADHWTS0 ADHWTS1 TM Confidential and Proprietary40 Trigger Multiplexing (TRGMUX) TM Confidential and Proprietary41 Trigger Multiplexing (TRGMUX continued) TM Confidential and Proprietary42 FlexTimer Module FTM

36、source clock is selectable with prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 from Busclock FTM has a 16-bit counter 2 up to 8 channels (inputs/outputs) The counting can be up or up-down Each channel can be configured for input capture, output compare, or PWM generation Input filter can be sele

37、cted for some channels New combined mode to generate a PWM signal (with independent control of both edges of PWM signal) Complementary outputs, include the deadtime insertion Software control of PWM outputs Up to 4 fault inputs for global fault control The polarity of each channel is configurable Th

38、e generation of an interrupt per channel input capture/compare, counter overflow, at fault condition Synchronized loading of write buffered FTM registers Write protection for critical registers Backwards compatible with TPM on other Freescale MCUs Dual edge capture for pulse and period width measure

39、ment Quadrature decoder with input filters, relative position counting and interrupt on Position count or capture of position count on external event TM Confidential and Proprietary43 Compatibility TM Confidential and Proprietary44 KEA to KFA Compatibility The KFA series will be 100% compatible with

40、in the KFA family Eg KFA512 lqfp 100 is identical to the KFA1M lqfp100 The KFA series will be pin compatible with the KEA range, with the following exceptions: The KFAxxx 64 pin device will have the VrefH bonded out on pin 9. On the KEA devices, pin 9 was VrefL Rationale for change: VrefH offers mor

41、e useful application functionality The KFAxxx devices will offer increased functionality, hence multiple new alternate levels of multiplexing will be available The 100 pin device is new to the family, hence there is no compatibility legacy requirements For clarity, the 8 high drive pins on the KEA w

42、ill also be present in the same positions on the KFA. TM Confidential and Proprietary45 Compatible 64lqfp pin-out to the KEA series TM Confidential and Proprietary46 Communication peripherals TM Confidential and Proprietary47 Low Power SPI (LPSPI) The LPSPI is a low power Serial Peripheral Interface

43、 (SPI) module that supports an efficient interface to an SPI bus as a master and/or a slave. The LPSPI can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses. Main features: Command/transmit F

44、IFO of 4 words. Receive FIFO of 4 words. Host request input can be used to control the start time of an SPI bus transfer. TM Confidential and Proprietary48 Low Power IIC (LPI2C) The LPI2C is a low power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a mas

45、ter and/or a slave. The LPI2C can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses. The LPI2C implements logic support for standard-mode, fast- mode and fast-mode plus modes of operation. It

46、 also supports high speed mode, supporting either complementary drive or current source pullup depending on what pin is used. The LPI2C module also complies with the System Management Bus (SMBus) Specification, version 2. TM Confidential and Proprietary49 LPUART Features of the LPUART module include

47、: Full-duplex, standard non-return-to-zero (NRZ) format Programmable baud rates (13-bit modulo divider) with configurable oversampling ratio from 4x to 32x Transmit and receive baud rate can operate asynchronous to the bus clock: Baud rate can be configured independently of the bus clock frequency S

48、upports operation in Stop modes Interrupt, DMA or polled operation Hardware parity generation and checking Programmable 8-bit, 9-bit or 10-bit character length Programmable 1-bit or 2-bit stop bits Independent FIFO structure for transmit and receive Hardware flow control support for request to send

49、(RTS) and clear to send (CTS) signals Three receiver wakeup methods (Idle line, Address mark, Receive data) Automatic address matching to reduce ISR overhead: Address mark matching Idle line address matching Address match start, address match end Optional 13-bit break character generation / 11-bit b

50、reak character detection Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle characters Selectable transmitter output and receiver input polarity TM Confidential and Proprietary50 FlexCAN3 Architecture Full Implementation of the CAN protocol specification, Version 2.0B F

51、lexible Message Buffers (16) of zero to eight bytes data length MB each configurable as Rx or Tx, all supporting standard and extended messages Individual Rx Mask Registers per Message Buffer Full featured Rx FIFO with storage capacity for 6 frames and internal pointer handling DMA request for Rx FI

52、FO Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 8 extended, 16 standard or 32 partial (8 bits) IDs, with individual masking capability Programmable clock source to the CAN Protocol Interface, either bus clock or crystal oscillator Programmable transmission priority

53、scheme: lowest ID, lowest buffer number or highest priority Time Stamp based on 16-bit free-running timer CAN FD support added to cut2.0 TM Confidential and Proprietary51 KFA512 FlexCAN3 enhancements Enhanced Feature DMA Request added to FlexCAN RxFIFO Allows CPU longer time to service the received

54、CAN messages. With the DMA connected the depth of the FIFO can be kept small RxFIFO Control Write_Pointer Read_Pointer 0 1 2 3 4 5 RxFIFO System DMA DMA Req DMA Ack System RAM TM Confidential and Proprietary52 CAN FD Support CAN FD stands for CAN with Flexible Data-Rate CAN FD is a variant of CAN pr

55、oposed by Bosch to: Increase the bit rate of the data portion of a CAN message (Up to 1-8Mbps) Increase the number of data bytes that can be sent in a single CAN message to up to 64 bytes (vs standard 8 bytes) CAN FD initial use case will be for end of line programming. As memory sizes in the car ar

56、e increasing, a faster means of programming the car is needed to reduce end of line programming costs. TM Confidential and Proprietary53 Flex IO TM Confidential and Proprietary54 “FlexIO” - Flexible input and output peripheral Highly configurable module & wide range functionality Emulation of standa

57、rd communication interfaces Supporting a wide range of protocols and peripherals including: UART I2C SPI I2S LCD RGB CMT (Carrier modulator transmitter) PWM/Waveform generation SWD (Single wire debug) Programmable logic for complex output generation (interaction between internal and external modules

58、) Low software/CPU overhead (a bit more overhead than dedicated peripheral IP) Optional to continue operating in debug Optional to continue operating under stop modes Support of polling/interrupt/DMA (RX/TX) operation TM Confidential and Proprietary55 TM Confidential and Proprietary56 Driver is divi

59、ded into two parts Main low level driver Initialization of peripheral Basic setting of timers and shifters Writing and reading to the register Sub drivers for each use case Focused on emulation of the peripheral (SPI, UART ) Allow using more instances of one driver Application can use both of driver

60、 layers Callback function implemented TM Confidential and Proprietary57 Bare metal drivers: http:/:81/mcuapps/L4KS_AppsVal/KLx3DriversManual/index.html FlexIO communication protocols emulation usecases: http:/:81/mcuapps/L4KS_AppsVal/AppsValDoc/index.html TM Confidential and Proprietary58 FlexIO Exa