成果电设2launchpad培训for40k v06

1、MSP430 | Ultra-Low Power is in our DNA Getting Started with the MSP430 LaunchPad Agenda Introduction to Value Line Code Composer Studio CPUX and Basic Clock Module Interrupt and GPIO TimerA and WDT+ Low-Power Optimization ADC10 and Comparator_A+ Serial Communications Grace Capacitive Touch Solution

2、MSP430 Released Devices Ultra-Low Power Worlds Lowest Power MCU Ultra-Low Power Active Mode 7 Low Power Modes Instant Wakeup All MSP430 devices are Ultra-Low Power Integration Intelligent Analog / Erased calibration data? Trap! BCSCTL1 = CALBC1_1MHZ; / Set range DCOCTL = CALDCO_1MHZ; / Set DCO step

3、+ modulation G2xx1 devices have 1MHz DCO constants only. Higher frequencies must be manually calibrated G2xx2 / Set range DCOCTL = _;/ Set DCO step + modulation BCSCTL3 |= LFXT1S_2;/ Set LFXT1 Reference Users Guide, Datasheet / Set MCLK Lab 2: BCSCTL2 in 2xx User Guide Lab 2: BCSCTL2 in MSP430G2453

4、head file Agenda Introduction to Value Line Code Composer Studio CPUX and Basic Clock Module Interrupt and GPIO TimerA and WDT+ Low-Power Optimization ADC10 and Comparator_A+ Serial Communications Grace Capacitive Touch Solution Interrupts and the Stack Entering Interrupts Any currently executing in

5、struction is completed The PC, which points to the next instruction, is pushed onto the stack The SR is pushed onto the stack The interrupt with the highest priority is selected The interrupt request flag resets automatically on single-source flags; Multiple source flags remain set for servicing by

6、software The SR is cleared; This terminates any low-power mode; Because the GIE bit is cleared, further interrupts are disabled The content of the interrupt vector is loaded into the PC; the program continues with the interrupt service routine at that address Vector Table Interrupt SourceInterrupt F

7、lag System Interrupt Word AddressPriority Power-up External Reset Watchdog Timer+ Flash key violation PC out-of-range PORIFG RSTIFG WDTIFG KEYV Reset0FFFEh31 (highest) NMI Oscillator Fault Flash memory access violation NMIIFG OFIFG ACCVIFG Non-maskable Non-maskable Non-maskable 0FFFCh30 0FFFAh29 0FF

8、F8h28 Comparator_A+CAIFGmaskable0FFF6h27 Watchdog Timer+WDTIFGmaskable0FFF4h26 Timer_A3TACCR0 CCIFGmaskable0FFF2h25 Timer_A3TACCR1 CCIFG TAIFG maskable0FFF0h24 0FFEEh23 0FFECh22 ADC10ADC10IFGmaskable0FFEAh21 USIUSIIFG USISTTIFG maskable0FFE8h20 I/O Port P2 (2)P2IFG.6 P2IFG.7 maskable0FFE6h19 I/O Por

9、t P1 (8)P1IFG.0 to P1IFG.7 maskable0FFE4h18 0FFE2h17 0FFE0h16 Unused0FFDEh to 0FFCDh15 - 0 ISR Coding #pragma vector=WDT_VECTOR _interrupt void WDT_ISR(void) IE1 / disable interrupt IFG1 / clear interrupt flag WDTCTL = WDTPW + WDTHOLD; / put WDT back in hold state BUTTON_IE |= BUTTON; / Debouncing c

10、omplete #pragma vector - the following function is an ISR for the listed vector _interrupt void - identifies ISR name No special return required Controlling GPIO Ports P1DIR |= BIT4; P1SEL |= BIT4; P1DIR |= BIT0; P1OUT |= BIT0; 26 Input Register PxIN Output Register PxOUT Direction Register PxDIR Fu

11、nction Select PxSEL Interrupt Edge PxIES Interrupt Enable PxIE Interrupt Flags PxIFG For GPIO Int Function Select PxREN Function Select PxSEL2 GPIO Register GPIO Code Example Pin Muxing Each pin has multiple functions Register bits select pin function See device specific datasheet Lab3: GPIO Lab3 Se

12、tup P1.3 to Button Setup P1.0 to LED control LED toggle with Button Lab 3: P1DIR |= BIT0; / Set P1.0 to output direction P1IES |= BIT3; / P1.3 Hi/lo edge _ / P1.3 IFG cleared _ |= BIT3; / P1.3 interrupt / Port1 interrupt service routine #pragma vector = _ _interrupt void Port_1(void) / Port1 interru

13、pt service routine P1OUT = BIT0; / P1.0 = toggle _ / P1.3 IFG cleared Agenda Introduction to Value Line Code Composer Studio CPUX and Basic Clock Module Interrupt and GPIO TimerA and WDT+ Low-Power Optimization ADC10 and Comparator_A+ Serial Communications Grace Capacitive Touch Solution Timer_A Asy

14、nchronous 16-Bit timer/counter Continuous, up-down, up count modes Multiple capture/compare registers PWM outputs Interrupt vector register for fast decoding Can trigger DMA transfer On all MSP430s 70 Timer_A Counting Modes 0FFFFh 0h CCR0 Stop/Halt Timer is halted Up Timer counts between 0 and CCR0

15、0FFFFh 0h Continuous Timer continuously counts up 0FFFFh 0h CCR0 UP/DOWN Mode Up/Down Timer counts between 0 and CCR0 and 0 CCR Count Compare Register 71 Timer_A Interrupts TACCR1 CCIFG TACCR2 CCIFG TAIFG TIMERA1_VECTORTAIV TACCR1, 2 and TA interrupt flags are prioritized and combined using the Time

16、r_A Interrupt Vector Register (TAIV) into another interrupt vector TACCR0 CCIFGTIMERA0_VECTOR The Timer_A Capture/Comparison Register 0 Interrupt Flag (TACCR0) generates a single interrupt vector: Your code must contain a handler to determine which Timer_A1 interrupt triggered No handler required 72

17、 TAIV Handler Example #pragma vector = TIMERA1_VECTOR _interrupt void TIMERA1_ISR(void) switch(_even_in_range(TAIV,10) case 2 : / TACCR1 CCIFG P1OUT = 0 x04; break; case 4 : / TACCR2 CCIFG P1OUT = 0 x02; break; case 10 : / TAIFG P1OUT = 0 x01; break; 0 xF814 add.w / Stop the dog . . WDT: Interval Ti

18、mer Function No PUC issued when interval is reached If WDTIE and GIE set when interval is reached, a WDT interval interrupt generated instead of reset interrupt Selectable intervals Lab4: Timer and Interrupts Lab4 Use TimerA to implement Lab2 Configure Timer_A3 Count Cycle: 5100 Occurs a interrupt w

19、hen TAR =100 Lab 4: / Configure TimerA TACTL = _; / Source: ACLK, UP mode CCR0 = 5100; /Timer count 5100 CCR1 = 100; /Timer count 100 CCTL0 = CCIE; /CCR0 interrupt enabled CCTL1 = CCIE; /CCR1 interrupt enabled / Timer A0 interrupt service routine #pragma vector = _ _interrupt void Timer_A0(void) / T

20、imer A1 interrupt service routine #pragma vector = _ _interrupt void Timer_A1(void) Agenda Introduction to Value Line Code Composer Studio CPUX and Basic Clock Module Interrupt and GPIO TimerA and WDT+ Low-Power Optimization ADC10 and Comparator_A+ Serial Communications Grace Capacitive Touch Soluti

21、on Ultra Low Power Feature MSP430 designed for ULP from ground up Peripherals optimized to reduce power and minimize CPU usage Intelligent, low power peripherals can operate independently of CPU and let the system stay in a lower power mode longer Ultra-Low Power Is In Our DNA Multiple operating mod

22、es 100 nA power down (RAM retained) 0.3 A standby 110 A / MIPS from RAM 220 A / MIPS from Flash Instant-on stable high-speed clock 1.8 - 3.6V single-supply operation Zero-power, always-on BOR 50nA pin leakage CPU that minimizes cycles per task Low-power intelligent peripherals ADC that automatically

23、 transfers data Timers that consume negligible power 100 nA analog comparators Performance over required operating conditions Ultra-Low Power Activity Profile Minimize active time Maximize time in Low Power Modes Interrupt driven performance on-demand with 1s wakeup time Always-On, Zero-Power Browno

24、ut Reset (BOR) Active Low Power Mode Average Off All Clocks Off 100nA Stand-by DCO off ACLK on 0.3A LPM3 RTC function LCD driver RAM/SFR retained CPU Off DCO on ACLK on 45A MSP430 Low Power Modes LPM0 LPM4 RAM/SFR retained Active DCO on ACLK on 220A 1s 1s Specific values vary by device BOR is enable

25、d in all modes Low Power Mode Configuration Active Mode 0 0 0 0 250uA LPM0 0 0 0 1 35uA LPM3 1 1 0 1 0.8uA LPM4 1 1 1 1 0.1uA bis.w #CPUOFF,SR ; LPM0 R2/SR Reserved C SCG1 SCG0 ZNGIE CPU OFF OSC OFF V LPM in Assembly 34 ORG 0F000h RESET mov.w #300h,SP mov.w #WDT_MDLY_32, / initialize Watchdog Timer

26、while(1) _bis_SR_register(LPM3_bits + GIE); / Enter LPM3, enable interrupts activeMode(); / in active mode. Do stuff! #pragma vector=WDT_VECTOR _interrupt void watchdog_timer (void) _bic_SR_register_on_exit(LPM3_bits); / Clear LPM3 bits from 0(SR), Leave LPM3, enter active mode = LPM3 + RTC_Function

27、 0.80A + 250A * 100s 1000000s 0.80A + 0.030A = 0.83A Time 1mA 1A 100A 10A / Partial RTC_Function incrementseconds(); incrementminutes(); incrementhours(); / 10-yr Embedded Real-Time Clock Low-Power Operation Power-efficient MSP430 apps: Minimize instantaneous current draw Maximize time spent in low

28、power modes The MSP430 is inherently low-power, but your design has a big impact on power efficiency Proper low-power design techniques make the difference “Instant on” clock 100% CPU Load Move Software Functions to Peripherals MCU P1.2 / Endless Loop for (;) P1OUT |= 0 x04; / Set delay1(); P1OUT /

29、Reset delay2(); / Setup output unit CCTL1 = OUTMOD0_1; _BIS_SR(CPUOFF); Zero CPU Load 47 Power Manage Internal Peripherals P1OUT |= 0 x02; / Power divider CACTL1 = CARSEL + CAREF_2 + CAON; / Comp_A on if (CAOUT / Fault else P1OUT P1OUT / de-power divider CACTL1 = 0; / Disable Comp_A Comparator_A 48

30、Op-amp with shutdown can be 20 x lower total power 0.01uA = Shutdown 20uA = Active - 0.06uA = Average 1uA = Quiescent 1uA = Active - 1uA = Average Power Manage External Devices 49 Unused Pin Termination Digital input pins subject to shoot-through current Input voltages between VIL and VIH cause shoo

31、t-through if input is allowed to “float” (left unconnected) Port I/Os should Driven as outputs Be driven to Vcc or ground by an external device Have a pull-up/down resistor Lab5: Low Power Mode Lab5 Optimize Lab4 to implement LPM Lab 5: _BIS_SR(_);/Enter Low Power Mode; Enter Low Power Modes with ju

32、st 1 line of code! Agenda Introduction to Value Line Code Composer Studio CPUX and Basic Clock Module Interrupt and GPIO TimerA and WDT+ Low-Power Optimization ADC10 and Comparator_A+ Serial Communications Grace Capacitive Touch Solution Fast Flexible ADC10 10-bit 8 channel SAR ADC 6 external channe

33、ls Vcc and internal temperature 200 ksps+ Selectable conversion clock Autoscan Single Sequence Repeat-single Repeat-sequence Internal or External reference Timer-A triggers Interrupt capable Data Transfer Controller (DTC) Auto power-down Direct Transfer Controller Data Transfer Controller Sample Tim

34、ing Reference must settle for 30uS Selectable hold time 13 clock conversion process Selectable clock source - ADC10OSC (5MHz) - ACLK - MCLK - SMCLK 70 Cycles / Sample Fully Automatic Autoscan + DTC Performance Boost Data2 Data1 Data0 Data2 ADC DTC AUTO / Autoscan + DTC _BIS_SR(CPUOFF); / Software Re

35、spRes+ = ADC10MEM; ADC10CTL0 if (pRes 0;CNT-) P2OUT if (SR SR = SR 1; if (P2IN P2OUT |= SCLK; P2OUT USI Reduces CPU Load for SPI 425 Cycles 10 Cycles / Shift16_inout_USI USISR |= DATA; USICNT |= 0 x10; I2C Slave has as little as 4us from clock edge to data Traditional software-only solution allows t

36、ime for little else USI hardware enables practical and compliant I2C Code on MSP430 website 85 USCI Designed for Ultra-Low Power: wAuto-Start from any Low-Power Mode Two Individual Blocks: wUSCI_A: UART or SPI wUSCI_B: SPI or I2C Double Buffered TX/RX Baudrate/Bit Clock Generator: wAuto-Baud Rate De

37、tect wFlexible Clock Source RX glitch suppression DMA enabled Error Detection Recommended USCI initialization/re-configuration process is shown in your workbook. 88 USCI Enhanced Features New standard MSP430 serial interface Auto clock start from any LPMx Two independent communication blocks Asynchronous communication modes wUART standard and multiprocessor protocols wUART with automatic Baud rate detection (LIN support) wTwo modulators support n/16 bit timing wIrDA bit shaping encoder and decoder Synchronous communication modes wSPI (Master supports n/16 timings - Auto baud rate detec