关于单片机的英文文献

1、engin e-c on trolsystems,brak ing systems (ABS). applications that benefitperipheralfun cti onsset, such as automotive power-traincon trol,vehicleThe General Situation of AT89C51Microc on trollers are used in a multitude of commercial applicatio ns such as modems, motor-c on trol systems, air con di

2、ti oner con trol systems, automotive engine and amongothers. The high processing speed and enhanced peripheral set of these microc on trollers make them suitable for such high-speed event-based applications.However, these criticalapplicati on doma ins also require that these microc on trollers are h

3、ighly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollersboth at the component and at the system level.In telPlatformEngin eeri ng departme nt developed an object-orie ntedmulti-thr

4、eaded test environment for the validation of its AT89C51 automotive microco ntrollers. The goals of this en vir onment was not only to provide a robust testing environment for the AT89C51 automotive microc on trollers, but to develop an en vir onment which canbe easilyextended and reused for the val

5、idation of several other future microcontrollers.The environment was developed in conjunctionwithMicrosoft Foun dati on Classes (AT89C51). The paper describes the desig n and mecha nism of this test en vir onmen t, its in teract ions with various hardware/software en vir onmen tal comp onen ts, and

6、how to use AT89C51.1.1 In troduct ionThe 8-bitAT89C51 CHMOSnicrocontrollersare designed to handlehigh-speed calculations and fast input/output operations. MCS 51 microc on trollersare typically used for high-speed eve nt con trol systems.Commercial applications include modems,motor-control systems,

7、printers, photocopiers, air con diti oner con trol systems, disk drives, and medical instruments.The automotive industryuse MCS 51 microcontrollersinairbags, suspension systems, and antilock The AT89C51 is especially well suited to from its processing speed and enhanced on-chipdynamic suspension, an

8、tilockbraking, and stability control applications.Because of these critical applications, the market requires a reliablecost-effectivecontrollerwith a low interruptlatency response, abilityto service the high nu mber of time and eve nt drive n in tegrated peripherals needed in real time applications

9、, and a CPUWith above average processing power in a single package. The financialand legal risk of having devicesthat operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohi

10、bitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the samecore and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with

11、a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testingof the controllersbe carried out at both thecomp onent level and system level un der worst case en vir onmen tal and voltage con diti ons. This complete and thorough validati on n

12、 ecessitates not only a well-defi ned process but also a proper en vir onment and tools to facilitate and execute the missi onsuccessfully.In telChan dlerPlatform Engin eeri ng group provides postsilic on system validati on (SV)of various micro-controllersand processors. The system validationprocess

13、 can be broke n into three major parts. The type of the device and its application requirements determine which types of testingareperformed on the device.1.2 The AT89C51 provides the follow ing sta ndard features:4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vec

14、tor two-level interrupt architecture, a full duple serial port, on-chip oscillator and clock circuitry.Inaddition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Modestops the CPUwhile allowing the RAM,

15、timer/counters,serialport and interrupt sys -tem to continue functioning.The Power-down Modesaves the RAMsontents but freezes the oscillator disabling all other chip fun cti ons un til the n ext hardware reset.1-3Pin DescriptionVCC Supply voltage.GND Grou nd.Port 0： Port 0 is an 8-bitopen-drain bi-d

16、irectional I/O port. As anoutput port, each pin can sink eight TTL in puts. Whe n 1s are writte n to port 0 pins, the pins can be used as high impeda nee in puts .Port 0 may also be con figured to be the multiplexed low order address/data bus duri ng accesses to exter nal program and data memory .In

17、 this modePO has internal pullups. Port 0 also receives the code bytes duri ng Flash program ming, and outputs the code bytes during program verification.External pullupsare required during program verification.Port 1: Port 1 is an 8-bit bi-directionalI/O port with internalpullups.The Port 1 output

18、buffers can sin k/source four TTL in puts. Whe n 1s are writte n to Port 1 pins they are pulled high by the internal pullups and can be used as in puts. As in puts, Port 1 pins that are exter nally being pulled low will source current (IIL) because of the internal pullups. Port1 also receives the lo

19、w-order address bytes during Flash programming and verificati on.Port 2 : Port 2 is an 8-bit bi-directional I/O port with internalpullups. The Port 2 output buffers can sin k/source four TTL in puts. Whe n 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as

20、in puts. As in puts, Port 2 pins that are exter nally being pulled low will source current (IIL) because of the internal pullups. Port2 emits the high-order address byte during fetches from external program memoryand during accesses to Port 2 pins that are externally being pulled low will source cur

21、rent (IIL) because of the internal pullups. Port 2 emits the high-order address byte duri ng fetches from exter nal program memoryand duri ng accesses to exter nal data memory that use 16-bit addresses (MOVXDPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesse

22、s to external data memory that use 8-bit addresses (MOVXRI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3: Port 3 is an 8-bit bi-directional I/O port with inte

23、rnalpullups. The Port 3 output buffers can sin k/source four TTL in puts. Whe n 1s are writte n to Port 3 pi ns they are pulled high by the internal pullups and can be used as in puts. As in puts, Port 3 pins that are exter nallybeingpulled low will source curre nt (IIL) because of the pullups.Port

24、3 also serves the functions of various special feature soft the AT89C51 as listed below:RST Reset in put. A high on this pin for two machi ne cycles while the oscillator is running resets the device.ALE/PROG Address Latch Enable output pulse for latching the low byte of the address duri ng accesses

25、to exter nal memory. This pin is also the program pulse in put (PROG)duri ng Flash program ming. In no rmal operati on ALE is emitted at a constant rate of 1/6 the oscillator frequency, and maybe used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped duri ng each

26、 access to exter nal Data Memory. If desired, ALE operati on can be disabled by sett ing bit 0 of SFR locatio n 8EH. With the bit set, ALEis active only during a MOVXr MOV(struction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in exte

27、rnal execution mode.PSEN Program Store Enable is the read strobe to external program memory. When theAT89C51 is executi ng code from exter nal program memory, PSEN is activated twice each machine cycle, except that two PSEN activati ons are skipped duri ng each access to exter nal data memory.EA/VPP

28、 External Access En able. EA must be strapped to GND in order to enable the device to fetch code from external program memorylocations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EAshould be strapped to VCCfor internalprogra

29、m executions. This pin all receives the 12-voltprogramming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1 In put to the in vert ing oscillator amplifier and in put to the internal clock operati ng circuit.XTAL2:Output from the inverting oscillator amplifier.

30、Oscillator CharacteristicsXTALI and XTAL2 are the in put and output, respectively, of an inverting amplifier which can be con figured for use as an on-chip oscillator, as shown in Figure 1. Either a quarts crystal or ceramic resonator maybe used. To drive the device from an external clock source, XT

31、AL2should be left unconnected while XTAL1is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the in put to the in ternalclock ingcircuitry is through adivide-by-two flip-flop, but minimumand maximum/oltage high and low time specifications mu

32、st be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the on chip peripherals rema in active. The mode is invoked by software. The content of the on-chip RAMnd all the special fun cti ons registersrema in un cha nged duri ng this mode. The idle modeca nbe term in ated by any

33、 en abled in terruptor by a hardware reset. It shouldbe no ted that whe n idle is termi nated by a hard ware reset, the deviceno rmally resumes program executi on, from where it left off, up to twomachine cycles before the internalreset algorithm takes control.On-chiphardware in hibitsaccess to inte

34、rnal RAMn this eve nt, but access to theport pins is not in hibited.To elim in ate the possibility of a n un expectedwrite to a port pin when Idle is terminated by reset, the instruction follow ing the one that inv okes Idle should not be one that writes to a port pin or to exter nal memory.Power-do

35、w n ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values un til the power-dow n mode is term in ated. The only exit from power-dow n is a hardware reset.

36、Reset redefi nes the SFR but does not cha nge the on-chip RAM. The reset should not be activated before VCC is restored to its no rmal operat ing level and must be held active long eno ugh to allow the oscillator to restart and stabilize. The AT89C51code memoryarray is programmedbyte-by byte in eith

37、er programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memorymust be erased using the Chip Erase Mode.2 Programmi ng AlgorithmBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming modetable and Fig

38、ure 3 and Figure 4. To program the AT89C51, take the follow ing steps.1. In put the desired memorylocatio n on the address lin es.2. In put the appropriate data byte on the data lin es. 3. Activate the correct comb in ati on of con trol signals. 4. Raise EA/VPP to 12V for the high-voltage programmin

39、g mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, cha nging the address and data for the entire array or until the end of the object reached. Data Polling: The AT8

40、9C51features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result inthe complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle maybegin. Data P

41、olling may begin any time after a write cycle has been initiated.2.1Ready/Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to in dicate BUSY. P3.4 is pulled high aga in whe n program ming is done to in

42、 dicate READY.Program Verify:If lock bits LB1 a nd LB2 have not bee n programmed, the programmedcode data can be read back via the address and data lines for verification.The lock bits cannot be verified directly.Verificationof the lock bitsis achieved by observing that their features are enabled.2.

43、2 Chip Erase:The en tire Flash array is erased electrically by using the propercomb in ati on of con trol sig nals and by holdi ng ALE/PROdbw for 10 ms. The code array is written with all“ 1 ” s. The chip erase operation must beexecuted before the code memory can be re-programmed.2.3 Read ing the Si

44、g nature Bytes:The sig nature bytes are read by the same procedure as a no rmal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned areas follows :(030H) = 1EH in dicates man ufactured by Atmel(031H) = 51H in dicates 89C51(032H

45、) = FFH in dicates 12V programmi ng(032H) = 05H in dicates 5V programmi ng2.4 Programmi ng In terfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate comb in ati on of con trol sig nals.The writeoperationcycle is self timed and once initia

46、ted, willautomatically time itself to completi on.A microcomputer in terfaceconverts in formatio n betwee n two forms. Outside the microcomputer the in formati on han dled by an electr onicsystem exists as a physical sig nal,but within the program, it is represented numerically. The function of any

47、in terfacecan be broke n dow n into a nu mber of operati ons which modifythe data in some way, so that the process of conv ersi on betwee n theexternal and internal forms is carried out in a number of steps. An an alog-to-digital con verter is used to convert a con ti nu ously variable signal to a c

48、orresponding digital form which can take any one of a fixed nu mber of possible binary values. If the output of the tran sducer does not vary con ti nu ously, no ADC is n ecessary .In this case the sig nal con diti oningsect ion must convert the incoming sig nal to a form which canbe conn ected dire

49、ctly to the n ext part of the in terface,the in put/outputsecti on of the microcomputer itself. Output in terfaces take a similar form, the obvious differenee being that here the flow of information is in the opposite directi on; it is passed from the program to the outside world.In this case the pr

50、ogram may call an output subroutine which supervises the operati on of the in terface and performs the scali ng nu mbers which may be needed fordigital-to-analogconverter.This subroutinepassesin formati on in tur n to an output device which produces a corresp onding electrical sig nal, which could b

51、e conv erted in to an alog form using a DAC. Fin ally the sig nal is con diti oned to a form suitable for operati ng an actuator. The signals used within microcomputer circuits are almost always too small to be connected directly to the outside world ” and some kind of in terface must be used to tran slate them to a more appropriate form. The desig n of secti on