设计一个补码定点小数乘法运算器

1、姓名：何飞龙 学号设计一个补码定点小数乘法运算器。设被，乘数，积，均为补码形式的定点小数。start是启动信号，down是除法完成信号，overflow是“溢出”报警信号，reset是清零信号，clock是时钟信号。请给出此除法器的VHDL功能描述，并编写测试向量文件，通过分析模拟结果验证设计的正确性。（X 补=1.0011，Y补=1.0101）程序代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY mult5 ISgeneric ( n: integer

2、 :=5; m: integer :=9 ); PORT(start,reset,clock: IN STD_LOGIC;-kaishi,fuwei,shizhongdone,overflow: OUT STD_LOGIC;-wancheng,yichuy,x: IN STD_LOGIC_VECTOR(n DOWNTO 1);-bei cheng shu,chengshup: OUT STD_LOGIC_VECTOR(m DOWNTO 1);-shuchuEND ENTITY mult5;ARCHITECTURE behav OF mult5 IS SIGNAL ry: STD_LOGIC_V

3、ECTOR(n DOWNTO 1); - SIGNAL pp: STD_LOGIC_VECTOR(m+1 DOWNTO 0);- SIGNAL state: integer RANGE 0 TO 5;-BEGIN PROCESS(reset,clock) VARIABLE temp: STD_LOGIC_VECTOR(n+1 DOWNTO 1);BEGIN IF reset=0 THENry 0);pp 0);state = 0;done ry = y; pp = 00000 & x & 0; IF start= 1 THEN state IF pp(1 DOWNTO 0) = 01 THEN

4、 temp := (pp(m+1) & pp(m+1 DOWNTO 6) + (ry(n) & ry);ELSIF pp(1 DOWNTO 0) = 10 THEN temp:=(pp(m+1) & pp(m+1 DOWNTO n+1)+NOT(ry(n) & ry) + 1;ELSE temp := (pp(m+1) & pp(m+1 DOWNTO n+1); END IF;p=temp(n DOWNTO 1) & pp(n DOWNTO 2); if temp(n+1)=1 then overflow =1; else overflow =0; end if;done = 1;state

5、IF pp(1 DOWNTO 0) = 01 THEN temp := (pp(m+1) & pp(m+1 DOWNTO n+1) + ( ry(n) & ry);-01 +BELSIF pp(1 DOWNTO 0)=10 THEN temp := (pp(m+1) & pp(m+1 DOWNTO n+1) + NOT(ry(n) & ry) + 1;-10-BELSE temp := (pp(m+1) & pp(m+1 DOWNTO n+1); END IF;pp = temp & pp(n DOWNTO 1); -Cyou yistate = state + 1; END CASE; EN

6、D IF; END PROCESS;END behav;编译综合:运行结果：RTL电路：2. 设计一个正数定点小数除法运算器。设被除数，除数，商，余数，均为正数。start是启动信号，down是除法完成信号，overflow是“溢出”报警信号，reset是清零信号，clock是时钟信号。请给出此除法器的VHDL功能描述，并编写测试向量文件，通过分析模拟结果验证设计的正确性。原码恢复余数法或原码不恢复余数法（加减交替法）。程序代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY div

7、i ISgeneric ( n: integer :=5);PORT(start,reset,clock: IN STD_LOGIC;done, overflow: OUT STD_LOGIC;x: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);-chu shuy: IN STD_LOGIC_VECTOR(n+n-2 DOWNTO 0);-bei chu shuq, r: OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0);-shang, yu shuEND ENTITY divi;ARCHITECTURE behav OF divi IS SIGNAL

8、 rx: STD_LOGIC_VECTOR(n DOWNTO 0); SIGNAL ry: STD_LOGIC_VECTOR(n DOWNTO 0); SIGNAL rq: STD_LOGIC_VECTOR(n-1 DOWNTO 0); SIGNAL flag: STD_LOGIC; SIGNAL state: integer RANGE 0 TO 7;BEGIN PROCESS(reset,clock) VARIABLE rmd: STD_LOGIC_VECTOR(n DOWNTO 0);-yushu VARIABLE sq: STD_LOGIC;-shangshangBEGIN IF re

9、set=0 THENry 0);rx 0);rq 0);overflow = 0;state = 0 ;flag = 1;done = 0; rx = 00 & x(n-2 DOWNTO 0); ry = 00 & y(n+n-3 DOWNTO n-1); rq flag = 1;done = 0; rx = 00 & x(n-2 DOWNTO 0); ry = 00 & y(n+n-3 DOWNTO n-1); rq = y(n-2 DOWNTO 0) & 0;IF start= 1 THEN state rmd := ry - rx;IF rmd(n DOWNTO n-1) = 00 TH

10、EN overflow = 1; state = 0; ELSE sq := 0; flag = 0; END IF;ry(n DOWNTO 0) = rmd(n-1 DOWNTO 0) & rq(n-1);rq(n-1 DOWNTO 0) = rq(n-2 DOWNTO 0) & sq; state IF flag = 1 THEN rmd := ry - rx;ELSE rmd := ry + rx; END IF;IF rmd(n DOWNTO n-1) = 00 AND (ryrx) THEN sq := 1; flag = 1;ELSE sq := 0; flag = 0; END

11、IF;rq(n-1 DOWNTO 0) = rq(n-2 DOWNTO 0) & sq; state IF rq(0) = 0 THEN q = rq ; r = ry(n-1 DOWNTO 0); done = 1; state = 0 ;ELSE ry = ry + rx; state q = rq ; r = ry(n-1 DOWNTO 0); done = 1; state IF flag = 1 THEN rmd := ry - rx;ELSE rmd := ry + rx; END IF;IF rmd(n DOWNTO n-1) = 00 AND (ryrx) THEN sq := 1; flag = 1;ELSE sq