数字电路正向设计流程概述

1、摘要作者在本文中，通过一个设计实例，向大家介绍了数字电路从前端到后端正向设计的一般流程。本文中的实例要求设计者设计一个四位ALU，为了让读者了解硬件描述语言代码的风格及其对综合和布局布线的影响，作者在本文中使用了两套风格的代码。但由于作者从事IC设计的经验有限，所以两套方案都没有成功，一个方案（无层次化设计）夭折于综合后，另一个方案（层次化设计）失败于布局布线后。但从让大家了解数字电路正向设计流程的目的来说，此实例还是很好地达到了预期的目标。可以说，这是一篇带你入门的文章，本文适合于所有数字电路初级设计人员。在接下来的一部分，作者按照数字电路正向设计的一般流程，结合软件（Cadence, Sy

2、nopsys）的使用，从几个方面向大家介绍了在工作站上的设计方法和情况。设计流程介绍1. 硬件描述语言的输入1.1真值表1.1.1代码一真值表1.1.2代码二真值表1.2结构图1.2.1代码一结构图1.2.2代码二结构图1.3代码1.3.1代码一 (无层次)1.3.1.1 ALU1.3.1.2 ALU_tb1.3.2代码二 (层次化)1.3.2.1 Decoder1.3.2.2 Fout_BIT1.3.2.3 Fout_BIT_ALU1.3.2.4 Single_BIT1.3.2.5 TOP1.3.2.6 ALU_tb2. 综合前的编译、仿真2.1 CASE 12.1.1 Verilog_XL

3、2.1.1.1 TestBenchtimescale 1ns/1ns/Time Unit & Precisionmodule ALU_tb;/List Ports To be Simulatedreg 2:0 S;reg 3:0 OPERAND_A,OPERAND_B;reg CO;reg 7:0 test;wire 3:0 ALU_RESULT;/Top ModuleALU u1 (.S(S),.A(OPERAND_A),.B(OPERAND_B),.F(ALU_RESULT),.Cin(CO);/FOR Simulationinitialbegin for ( test = 0; test

4、 = 8hfe; test = test+1) begin CO = test0; S2:0 = test3:1; OPERAND_A = test3:0; OPERAND_B = test7:4; #10; end $finish;end/ FOR XLinitialbegin $shm_open(ALU.shm); $shm_probe(AC);endendmodule2.1.1.2文件准备codes目录下是你的设计文件和测试文档runme.f文件：./codes/ALU_tb.v ./codes/ALU.v2.1.1.3 Start Upserver% verilog -f runme.

5、f +gui&1 132412.1.1.4 Next Steps2.1.1.5 WaveForm2.1.2 VCS2.1.2.1 TestBench/Time Unit & Precisiontimescale 1ns/1nsmodule ALU_tb;/List Ports To be Simulatedreg 2:0 S;reg 3:0 OPERAND_A,OPERAND_B;reg CO;reg 7:0 test;wire 3:0 ALU_RESULT;/Top ModuleALU u1 (.S(S),.A(OPERAND_A),.B(OPERAND_B),.F(ALU_RESULT),

6、.Cin(CO);/ FOR VCSinitialbegin ifdef vcd $display(nVCD+ onn); $vcdpluson; endifend/FOR Simulationinitialbegin for ( test = 0; test = 8hfe; test = test+1) begin CO = test0; S2:0 = test3:1; OPERAND_A = test3:0; OPERAND_B = test7:4; #10; end $finish;endendmodule2.1.2.2文件准备codes目录下是你的设计文件和测试文档runme.f文件：

7、./codes/ALU_tb.v ./codes/ALU.v2.1.2.3 Start Up/postprocessing modeserver% vcs f runme.f PP R +vcsd +define+vcdserver% vcs -f runme.f RPP/interactive modeserver% vcs -f runme.f -Mupdate -RINote: Environment variable $VCS_HOME (/synopsys/vcs6.0.1) overrides default location to find software (/usr/loca

8、l/VCS)* Using loader /usr/ccs/bin/ld instead of cc . Chronologic VCS (TM) Version 6.0.1 - Wed Jul 7 02:42:37 2004 Copyright (c) 1991-2001 by Synopsys Inc. ALL RIGHTS RESERVEDThis program is proprietary and confidential information of Synopsys Inc.and may be used and disclosed only as authorized in a

9、 license agreementcontrolling such use and disclosure.* Warning: ACC/CLI capabilities have been enabled for the entire design.For faster performance enable module specific capability in pli.tab fileParsing design file ./codes/ALU_tb.vParsing design file ./codes/ALU.vTop Level Modules: ALU_tbTimeScal

10、e is 1 ns / 1 ns2 modules to be compiled, 0 UDPs to be compiled. However, due to inlining, only 1 module needs to be compiled.recompiling module ALU_tb1 of 1 modules doneif -x ./simv ; then chmod -x ./simv; fi/usr/ccs/bin/ld -o ./simv /synopsys/vcs6.0.1/virsimdir/Solaris/vcdplus/vcs6_0/vcspli.o /syn

11、opsys/vcs6.0.1/sun_sparc_solaris_5.5.1/lib/crt1.o /synopsys/vcs6.0.1/sun_sparc_solaris_5.5.1/lib/crti.o /synopsys/vcs6.0.1/sun_sparc_solaris_5.5.1/lib/crtn.o 5NrI_d.o 5NrIB_d.o pZ0v_1_d.o -lnsl -lsocket -ldl /synopsys/vcs6.0.1/sun_sparc_solaris_5.5.1/lib/libvcs.a -lm -lc -ldl ./simv up to dateVirSim

12、 4.1.1.patch2 Virtual Simulator EnvironmentCopyright (C) 1993-2001 by Synopsys, Inc.Licensed Software. All Rights Reserved.Use virsim help_arg for usage information. help_arg: -help or -verilog_help or -vhdl_help or -epic_help2.1.2.4 Next Steps/postprocessing mode/interactive mode2.1.2.5 WaveForm/po

13、stprocessing mode/interactive mode2.2 CASE 22.2.1 Verilog_XL2.2.1.1 TestBenchtimescale 1 ns / 1 ns/Time Unit & Precisionmodule ALU_tb;/List Ports To be Simulatedreg 2:0 S;reg 3:0 OPERAND_A,OPERAND_B;reg CO;reg 11:0 test;wire 3:0 ALU_RESULT;/Top ModuleTOP u8(.S(S),.OPERAND_A(OPERAND_A),.OPERAND_B(OPE

14、RAND_B),.ALU_RESULT(ALU_RESULT),.CO(CO);/FOR Simulationinitialbegin for ( test = 0; test = 12hffe; test = test+1) begin CO = test0; S2:0 = test3:1; OPERAND_A = test7:4; OPERAND_B = test11:8; #50; end $finish;end/ FOR XLinitialbegin $shm_open(ALU.shm); $shm_probe(AC);endendmodule2.2.1.2文件准备codes目录下是你

15、的设计文件和测试文档runme.f文件：./codes/ALU_tb.v./codes/Decoder.v./codes/Four_BIT.v./codes/Four_BIT_ALU.v./codes/Single_BIT.v./codes/TOP.v2.2.1.3 Start Upserver% verilog -f runme.f +gui&2.2.1.4 WaveForm2.2.2 VCS2.2.2.1 TestBench/Time Unit & Precisiontimescale 1 ns / 1 nsmodule ALU_tb;/List Ports To be Simulated

16、reg 2:0 S;reg 3:0 OPERAND_A,OPERAND_B;reg CO;reg 11:0 test;wire 3:0 ALU_RESULT;/Top ModuleTOP u8 (.S(S),.OPERAND_A(OPERAND_A),.OPERAND_B(OPERAND_B),.ALU_RESULT(ALU_RESULT),.CO(CO);/ FOR VCSinitialbegin ifdef vcd / enable vcd dumping $display (nVCD+ dumping is turned onn); $vcdpluson; endifend/FOR Si

17、mulationinitialbegin for ( test = 0; test read_verilog ALU.vLoading verilog file /training/tr03/david_j/IC_test/test1/Syn/codes/ALU.vDetecting input file type automatically (-rtl or -netlist).Reading with Presto HDL Compiler (equivalent to -rtl option).Running PRESTO HDLCLoading db file /export/home

18、/synopsys/syn03/libraries/syn/standard.sldbLoading db file /export/home/synopsys/syn03/libraries/syn/gtech.dbLoading db file /training/tr03/david_j/IC_test/test1/Syn/Libs/csmc06core.dbCompiling source file /training/tr03/david_j/IC_test/test1/Syn/codes/ALU.vWarning: /training/tr03/david_j/IC_test/te

19、st1/Syn/codes/ALU.v:12: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)Statistics for case statements in always block at line 10 in file /training/tr03/david_j/IC_test/test1/Syn/codes/ALU.v=| Line | full/ parallel |=| 12 | auto/auto |=Presto compilation completed successfully.Current

20、design is now /training/tr03/david_j/IC_test/test1/Syn/codes/ALU.db:ALUALUdc_shell-t linkLinking design: ALUUsing the following designs and libraries: ALU, csmc06core (library)1dc_shell-t echo $target_librarycsmc06core.dbdc_shell-t echo $link_library* csmc06core.dbdc_shell-t echo $symbol_librarycsmc

21、06core.sdbdc_shell-t echo $search_path. /export/home/synopsys/syn03/libraries/syn /export/home/synopsys/syn03/dw/sim_ver ./Libs ./Scripts ./codesdc_shell-t list_libsLogical Libraries:-Library File Path- - -standard.sldb standard.sldb /export/home/synopsys/syn03/libraries/sygtech gtech.db /export/hom

22、e/synopsys/syn03/libraries/sycsmc06core csmc06core.db /training/tr03/david_j/IC_test/test1/Syn1dc_shell-t report_lib csmc06core Reports/csmc06core.rptdc_shell-t get_designsALUdc_shell-t get_portsS2, S1, S0, A3, A2, A1, A0, B3, B2, B1, B0, F3, F2, F1, F0, Cindc_shell-t get_netsS2, S1, S0, A3, A2, A1,

23、 A0, B3, B2, B1, B0, F3, F2, F1, F0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, *Logic1*, Cin, N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, N18, N19, N20, N21, N22, N23, N24, N25, N26, N27, N28, N29, N30, N31, N32, N33, N34, N35, N36, N37, N38, N39, N40, N4

24、1, N42, N43, N44, N45, N46, N47, N48, N49, N50, N51, N52, N53, N54, N55, N56, N57, N58, N59, N60, N61, N62, N63, N64, N65, N66, N67, N68, N69, N70.dc_shell-t all_inputsS2, S1, S0, Cin, A3, A2, A1, A0, B3, B2, B1, B0dc_shell-t all_outputsF3, F2, F1, F0dc_shell-t get_libsstandard.sldb, gtech, csmc06co

25、redc_shell-t report_attribute -pin get_pins csmc06core/AN02D1/A*Report : AttributeDesign : ALUVersion: 2003.06-SP1Date : Fri Jul 9 03:36:22 2004*Design Object Type Attribute Name Value-ALU A port capacitance 0.007631ALU A port fanout_load 0.996735ALU A port pin_used_in_function trueALU A port pin_cl

26、ass 0ALU A port pin_sense true1dc_shell-t report_attribute -pin get_pins csmc06core/IN01D1/YN*Report : AttributeDesign : ALUVersion: 2003.06-SP1Date : Thu Jul 8 21:44:46 2004*Design Object Type Attribute Name Value-ALU YN port max_fanout 4.000000ALU YN port function !(A)ALU YN port series_parallel t

27、rueALU YN port pin_function_class a1ALU YN port pin_function_id Ia1.0ALU YN port pin_class 1ALU YN port pin_sense false1dc_shell-t quitMemory usage for this session 17232 Kbytes.CPU usage for this session 5 seconds.Thank you.dc_shell-t exitMemory usage for this session 16008 Kbytes.CPU usage for thi

28、s session 5 seconds.Thank you.3.1.1.2.2运行命令server% dc_shell-t Behavioral Compiler (TM) DC Professional (TM) DC Expert (TM) DC Ultra (TM) FloorPlan Manager (TM) VHDL Compiler (TM) HDL Compiler (TM) Library Compiler (TM) Power Compiler (TM) DFT Compiler (TM) BSD Compiler DesignWare Developer (TM) Desi

29、gnPower (TM) Version 2003.06-SP1 for sparcOS5 - Aug 15, 2003 Copyright (c) 1988-2003 by Synopsys, Inc. ALL RIGHTS RESERVEDThis program is proprietary and confidential information of Synopsys, Inc.and may be used and disclosed only as authorized in a license agreementcontrolling such use and disclosu

30、re.Initializing.dc_shell-t source constraints.tclLoading db file /training/tr03/david_j/IC_test/test1/Syn/DB/1.dbCurrent design is now /training/tr03/david_j/IC_test/test1/Syn/DB/1.db:ALULinking design: ALUUsing the following designs and libraries: ALU, ALU, csmc06core (library)Resetting current des

31、ign ALUUsing operating conditions WORST found in library csmc06core.Design ALU: Using wire_load model 150kxabove found in library csmc06core.Warning: Design rule attributes from the driving cell will be set on the port. (UID-401)Warning: Design rule attributes from the driving cell will be set on th

32、e port. (UID-401)Warning: Design rule attributes from the driving cell will be set on the port. (UID-401)Warning: Design rule attributes from the driving cell will be set on the port. (UID-401)Warning: Design rule attributes from the driving cell will be set on the port. (UID-401)Warning: Design rul

33、e attributes from the driving cell will be set on the port. (UID-401)Warning: Design rule attributes from the driving cell will be set on the port. (UID-401)Warning: Design rule attributes from the driving cell will be set on the port. (UID-401)Warning: Design rule attributes from the driving cell w

34、ill be set on the port. (UID-401)Warning: Design rule attributes from the driving cell will be set on the port. (UID-401)Warning: Design rule attributes from the driving cell will be set on the port. (UID-401)Warning: Design rule attributes from the driving cell will be set on the port. (UID-401)Inf

35、ormation: Defining new variable MAX_INPUT_LOAD. (CMD-041)1dc_shell-t source run.tclInformation: Evaluating DesignWare library utilization. (UISN-27)=| DesignWare Library | Available |=| DesignWare-Basic | * | DesignWare-Foundation | |= Loading target library csmc06core Loading design ALU Beginning Resource Allocation (area only) - Allocating blocks in ALU Beginni