姜书艳数字逻辑设计及应用16

1、1 1chapter 6 combinational logic design chapter 6 combinational logic design practicespractices( (组合逻辑设计实践组合逻辑设计实践) )documentation standard and circuit timing (文档标准和电路定时文档标准和电路定时)commonly used msi combinational logic device (常用的中规模组合逻辑器件常用的中规模组合逻辑器件)digital logic design and application ( (数字逻辑设计及应用数

2、字逻辑设计及应用) )2 2decoder (译码器译码器)cascading binary decoders (译码器的级联译码器的级联)realize a logic circuit by using decoder (利用译码器实现逻辑电路利用译码器实现逻辑电路)review of last class (review of last class (内内容回顾容回顾) )digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )3 3n0n1n2n3en_l+5vd0_ld7_ld8_ld15_l用用74x13874x138

3、设计设计4-16译码器译码器思路：思路： 1616个输出需要个输出需要 片片74x13874x138？y0y7abcg1g2ag2by0y7abcg1g2ag2bu1u2 任何时刻只有任何时刻只有一片在工作。一片在工作。 4 4个输入中，个输入中，哪些位控制片选哪些位控制片选哪些位控制输入哪些位控制输入cascading binary decoders (级联二进制译码器）级联二进制译码器）4 4consider: how to make a 5-to-32 decoderconsider: how to make a 5-to-32 decoder with 3-to-8 decoder?

4、with 3-to-8 decoder? ( (思考：用思考：用74x13874x138设计设计 5 5-32 译码器译码器) )how many 74x138 chips to be usedhow many 74x138 chips to be usedwith 32 outputs?with 32 outputs?(32(32个输出需要多少片个输出需要多少片74x138 74x138 ？) )control that only one chip works in any timecontrol that only one chip works in any time( (控制任何时刻只有

5、一片工作控制任何时刻只有一片工作) ) use the enable inputs ( use the enable inputs (利用使能端利用使能端) )digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )5 5consider: how to make a 5-to-32 decoder consider: how to make a 5-to-32 decoder with 3-to-8 decoder?with 3-to-8 decoder? ( (思考：用思考：用74x13874x138设计设计 5 5-32

6、译码器译码器) )control inputs of three low-order bits of a 5-bit code word (5个输入的低个输入的低3位控制输入位控制输入)control chips of two high-order bits of a 5-bit code word (5个输入的高个输入的高2位控制片选位控制片选) use 2-to-4 decoder ( 利用利用 2-4 译码器译码器)图图637digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )6 6用译码器和逻辑门实现逻辑函数用译码器

7、和逻辑门实现逻辑函数zyxabcg1g2ag2by0y1y2y3y4y5y6y774x138f+5vf = (x,y,z) (0,3,6,7)当使能端有效时当使能端有效时yi = midigital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )7 7用译码器和逻辑门实现逻辑函数用译码器和逻辑门实现逻辑函数zyxabcg1g2ag2by0y1y2y3y4y5y6y774x138+5vff = (x,y,z) (0,3,6,7)digital logic design and application ( (数字逻辑设计及应用数字逻辑设计

8、及应用) )8 8decoder (译码器译码器)encoder (编码器编码器)(优先编码器的级联和应用优先编码器的级联和应用)review of last class (review of last class (内内容回顾容回顾) )cascading priority encodersdigital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )9 9a2a1a0gseoeii7i0a2a1a0gseoeii7i0q15_lq8_lq7_lq0_ly0y1y2y3gs2 2个个74x14874x148级联为级联为16164 4

9、优先编码器优先编码器1010输入：由输入：由8 86464，需需8 8片片74x14874x148每片优先级不同（怎样实现？）每片优先级不同（怎样实现？） 保证高位无输入时，次高位才工作保证高位无输入时，次高位才工作 高位芯片的高位芯片的eoeo端接次高位芯片的端接次高位芯片的eiei端端用用8-38-3优先编码器优先编码器74x14874x148级联为级联为64-664-6优先编码器优先编码器a2a1a0gseoeii7i0片间优先级的编码片间优先级的编码 利用第利用第9 9片片74x14874x148 每片的每片的gsgs端接到第端接到第9 9片的输入端片的输入端 第第9 9片的输出作为高

10、片的输出作为高3 3位（位（ra5ra5ra3ra3）片内优先级片内优先级片间优先级片间优先级 输出：输出：6 6位位低低3 3位位高高3 3位位8 8片输出片输出a2a2a0a0通过或门作为通过或门作为最终输出的低最终输出的低3 3位位ra2ra2ra0ra0digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )11 11decoders (译码器译码器)encoders (编码器编码器)three-state devices (三态器件三态器件)multiplexer (多路复用器多路复用器) 标准标准msi多路复用器多路

11、复用器 74x151、 74x153、74x157 扩展多路复用器扩展多路复用器 利用多路复用器实现逻辑函数利用多路复用器实现逻辑函数 多路分配器多路分配器 (demultiplexer) 利用带使能端的译码器利用带使能端的译码器 使能端作为数据输入端使能端作为数据输入端review of last class (review of last class (内内容回顾容回顾) )1212 10niiidmeny当使能端有效时，当使能端有效时， 10niiidmy最小项之和形式最小项之和形式enabcd0d1d2d3d4d5d6d7yy74x151实现逻辑函数实现逻辑函数 f = f = (a,

12、b,c)(a,b,c)(0,1,3,7)(0,1,3,7)cbavccf用多路复用器设计组合逻辑电路用多路复用器设计组合逻辑电路digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )1313思考：利用思考：利用74x15174x151实现逻辑函数实现逻辑函数f = f = (w,x,y,z)(w,x,y,z)(0,1,3,7,9,13,14)(0,1,3,7,9,13,14)降维：由降维：由4 4维维3 3维维shannons expansion theorems ( 香农展开定理香农展开定理 )1、f(1,x2,x3,xn)

13、 = f(0,x2,x3,xn)=0, 填填02、f(1,x2,x3,xn) = f(0,x2,x3,xn)=1， 填填13、f(1,x2,x3,xn)=1，f(0,x2,x3,xn)=0， 填填x14、f(1,x2,x3,xn)=0，f(0,x2,x3,xn)=1， 填填x1digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) ), 0(), 1(),(121121121xxfxxxfxxxxf 1414yzwx00 01 11 10000111101111111ywx00 01 11 100110zzzzz0思考：利用思考：

14、利用74x15174x151实现逻辑函数实现逻辑函数f = f = (w,x,y,z)(w,x,y,z)(0,1,3,7,9,13,14)(0,1,3,7,9,13,14)降维：由降维：由4 4维维3 3维维digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )1515enabcd0d1d2d3d4d5d6d7yy74x151vccyxwfz利用利用74x15174x151实现实现f = f = (w,x,y,z)(w,x,y,z)(0,1,3,7,9,13,14)(0,1,3,7,9,13,14)0 2 6 4 1 3 7

15、5 ywx00 01 11 100110zzzzz0digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )1616a binary decoder with an enable input can be used as a demultiplexer(利用带使能端的二进制译码器作为多路分配器利用带使能端的二进制译码器作为多路分配器)abcg1g2ag2by0y1y2y3y4y5y6y774x138dst0_ldst7_l数据输入数据输入 srcen_l利用利用74x13974x139实现实现2 2位位4 4输出多路分配器（输出

16、多路分配器（figure 6-65figure 6-65）dstsel0dstsel1dstsel2地址地址选择选择 enable input is connected to the data line enable input is connected to the data line ( (利用使能端作为数据输入端利用使能端作为数据输入端) )数据输入数据输入 srcen_l1717译码器译码器编码器编码器三态器件三态器件多路复用器多路复用器parity circuit (奇偶校验器奇偶校验器)comparator (比较器比较器) 奇校验：输入有奇数个奇校验：输入有奇数个1，输出为，输出

17、为1 偶校验：输入有偶数个偶校验：输入有偶数个1，输出为，输出为1 利用异或运算实现利用异或运算实现 9位奇偶发生器位奇偶发生器74x280 奇偶校验的应用奇偶校验的应用 检测代码在传输和存储检测代码在传输和存储 过程中是否出现差错。过程中是否出现差错。review of last class (review of last class (内内容回顾容回顾) )18189-bit odd/even parity generator 74x280 9-bit odd/even parity generator 74x280 (9 (9位奇偶校验发生器位奇偶校验发生器74x28074x280（p2

18、91 p291 图图5 57575）abcdefghievenodd74x280digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )1919parity-checking applicationsparity-checking applications( (奇偶校验的应用奇偶校验的应用) )用于检测代码在传输和存储过程中是否出现差错用于检测代码在传输和存储过程中是否出现差错aevenodd74x280hiaevenodd74x280hi发发端端收收端端db0:7db0:7error发端保证有偶数个发端保证有偶数个1 1收端收

19、端 odd odd 有效表示出错有效表示出错奇数奇数eveneven20206.9 comparator 6.9 comparator （比较器）（比较器）compare two binary words and indicate whether they are equal(比较比较2个二进制数值并指示其是否相等的电路个二进制数值并指示其是否相等的电路)comparator: check if two binary words are equal ( 等值比较器：检验数值是否相等等值比较器：检验数值是否相等 )magnitude comparator: compare their magni

20、tude (greater than, equal, less than) (数值比较器：比较数值的大小（数值比较器：比较数值的大小（,=,b（a=1, b=0）则）则 ab=1 可作为输出信号可作为输出信号 ab3)lt = eq gt = ( eq + gt )或或 (a3 = b3) (a2 = b2) (a1b1)或或 (a3 = b3)(a2 = b2)(a1 = b1) (a0b0)或或 (a3 = b3) (a2b2)a3 b3a2 b2a1 b1a0 b0 +digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用)

21、)262674x854-bit comparator 74x85 4-bit comparator 74x85 ( 4( 4位比较器位比较器74x85)74x85)a0a1a2a3altbinaeqbinagtbin级联输入，用于扩展级联输入，用于扩展altbout = (ab高位高位a高位高位=b高位高位 & a低位低位b低位低位abaeqbout = (a=b)aeqbinagtbout = (ab) + (a=b)agtbindigital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )2727serial expanding

22、comparatorsserial expanding comparators( (比较器的串行扩展比较器的串行扩展) )xd11:0yd11:03:07:411:8xy+5vabiaboa0a3b0b374x85abiaboa0a3b0b374x85abiaboa0a3b0b374x853 3片片74x8574x85构成构成1212位比较器位比较器低位低位高位高位digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )2828p0p1p2p3p4p5p6p78 8位比较器位比较器74x68274x682内部逻辑图：图内部逻辑图

23、：图6-826-82问题问题1：怎样表示以下输出？：怎样表示以下输出？ 高电平有效：高电平有效：p diff q 高电平有效：高电平有效：p eq q 高电平有效：高电平有效：p ge q 高电平有效：高电平有效：p lt q （ 图图6-81）gelt问题问题2：能否扩展？：能否扩展？注意：没有级联输入端注意：没有级联输入端digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )29293 3片片74x68274x682构成构成2424位比较器位比较器p0p7 p=qq0q7 pqp0p7 p=qq0q7 pqp0p7 p=q

24、q0q7 pq7:015:823:16p23:0q23:0peqqpgtqparalel expanding comparatorsparalel expanding comparators( (比较器的并行扩展比较器的并行扩展) )30306.10 adder (6.10 adder (加法器加法器) )half adder and full adderhalf adder and full adder（半加器和全加器）（半加器和全加器）0 0 0 00 1 0 11 0 0 11 1 1 0a bsco(半加器真值表半加器真值表)sum (相加的和相加的和): s = ab + ab =

25、a bcarry (向高位的进位向高位的进位)：co = ab0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1ci x ysco(全加器真值表全加器真值表)truth table of half addertruth table of full adderdigital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )3131scoxycis = x y cixy00100111cixy00 01 11 1001coxcico = + +yc

26、i= xy + (x+y)ci0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1ci x ysco全加器真值表全加器真值表6.10 adder (6.10 adder (加法器加法器) )6.10.1 half adders and full adders6.10.1 half adders and full adders（半加器和全加器）（半加器和全加器）truth table of full adderdigital logic design and application ( (数字逻辑设计及应

27、用数字逻辑设计及应用) )32326.10.2 ripple adders (6.10.2 ripple adders (串行进位加法器串行进位加法器) )(缺点：运算速度慢，有较大的传输延迟缺点：运算速度慢，有较大的传输延迟)tadd = txycout + (n-2)*tcincout + tcinsx yci cosx yci cosx yci cosx yci cosc1c2c3c4c0s0s1s2s3x0 y0x1 y1x2 y2x3 y3=0回顾：串行比较器回顾：串行比较器 improve speed: parallel adder (提高速度：并行加法器提高速度：并行加法器)di

28、sadvantage: slow, more propagation delaydigital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )3333x yci cosx yci cosx yci cosx yci cosc1c2c3c4c0s0s1s2s3x0 y0x1 y1x2 y2x3 y3x ycmpeqi eqox0y0x1y1xn-1yn-1eq1eq2eqneqn-11x ycmpeqi eqox ycmpeqi eqoan iterative comparator(串行比较器串行比较器)ripple adder(串行加

29、法器串行加法器)primary inputs( (主主 输输 入入) )primary outputs ( (主主 输输 出出) )boundaryinputs(边界边界输入输入)boundaryoutputs(边界边界输出输出)级联输出级联输出3434an iterative circuitan iterative circuit（迭代电路）（迭代电路）iterativeiterative：重复的：重复的, , 反复的反复的, , 数数 迭代的迭代的pici copopici copopici copoc0c1c2cnpo0po1pon-1主主 输输 出出pi0pi1pin-1主主 输输 入

30、入边边界界输输入入边边界界输输出出级联输出级联输出digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )35356.10.3 subtractors (6.10.3 subtractors (减法器减法器) ) 方法一：利用真值表化简设计减法器方法一：利用真值表化简设计减法器 二进制减法表（表二进制减法表（表2-32-3）d = x y bi bo = xy + xbi + ybi 方法二：利用加法器设计减法器方法二：利用加法器设计减法器（xy）相当于（）相当于（xy补）补） 对对y求补：逐位求反求补：逐位求反11x yci

31、cosx yci cosx yci cosb_lx0 y0x1 y1xn ynd0d1dndigital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )3636一位全加器：一位全加器：s = x y cici+1 = xy + (x+y)ci6.10.4 carry-lockahead adders 6.10.4 carry-lockahead adders ( (先行进位加法器先行进位加法器) )先行进位法先行进位法：第：第 i i 位的进位输入信号可以由该位以前位的进位输入信号可以由该位以前的各位状态决定。的各位状态决定。ci+1

32、 = (xiyi) + (xi+yi) ci= gi + pi ci进位产生信号进位产生信号进位传递信号进位传递信号0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1cix ysci+1全加器真值表全加器真值表digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )3737先行进位法先行进位法：第：第 i i 位的进位输入信号位的进位输入信号可以由该位以前的各位状态决定。可以由该位以前的各位状态决定。c0 = 0ci+1 = gi +

33、pi ci c0 = 0 c1 = g0+p0c0 c2 = g1+p1c1 = g1+p1(g0+p0c0) = g1+p1g0+ p1p0c0 cn = gn+pncn （图（图6-89）展开为展开为“与与- -或或”式：三级延迟式：三级延迟msi加法器加法器74x283图图6-87 6-88digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )6.10.4 carry-lockahead adders 6.10.4 carry-lockahead adders ( (先行进位加法器先行进位加法器) )383838adde

34、r example: dip-switch-based adding calculatorgoal: create calculator that adds two 8-bit binary numbers, specified using dip switchesdip switch: dual-inline package switch, move each switch up or downsolution: use 8-bit adder3939adder example: adder example: dip-switch-based dip-switch-based adding

35、calculatoradding calculatorsolution: use 8-bit adderdip switches10a7.a0b7.b0s7s08-bit carry-ripple addercoci0calcleds404040adder example: adder example: dip-switch-based dip-switch-based adding calculatoradding calculatorto prevent spurious(假的）假的） values from appearing at output, can place register

36、at outputactually, the light flickers from spurious values would be too fast for humans to detectbut the principle of registering outputs to avoid spurious values being read by external devices (which normally arent humans) applies here.4141adder example: adder example: dip-switch-based dip-switch-b

37、ased adding calculatoradding calculatordip switches10a7.a0b7b0s7s08-bit adder8-bit registercoci0calcledseclkld4242设计减法器设计减法器 方法一：利用真值表化简方法一：利用真值表化简 二进制减法表（表二进制减法表（表2-32-3）d = x y bi bo = xy + xbi + ybi 方法二：利用加法器设计减法器方法二：利用加法器设计减法器（xy）相当于（）相当于（xy补）补） 对对y求补：逐位求反求补：逐位求反11x yci cosx yci cosx yci cosb_lx

38、0 y0x1 y1xn ynd0d1dndigital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )434343adder/subtractoradder/subtractoradder/subtractor: control input determines whether add or subtractcan use 2x1 mux sub input passes either b or inverted balternatively, can use xor gates if sub input is 0, bs bits

39、pass through; if sub input is 1, xor inverts bs bits444444adder/subtractoradder/subtractorb7b6subadder s b inputs01n-bit 2x1n-bitaasbbsubadder cin4545adder/subtractor example: calculatoradder/subtractor example: calculatorprevious calculator used separate adder and subtractordip switches108-bit regi

40、stercalcledsefclkld88800888882x10110wiciaabbsscowo8-bit adder8-bit subtractor464646adder/subtractor example: calculatoradder/subtractor example: calculatorimprove by using adder/subtractor, and twos complement numbersdip switches108-bit register8-bit adder/subtractorsubcalcledsesabfclkld108888474747

41、subtractor example:subtractor example: dip-switch based dip-switch based adding/subtracting calculatoradding/subtracting calculatorextend earlier calculator exampleswitch f indicates whether want to add (f=0) or subtract (f=1)use subtractor and 2x1 mux484848subtractor example:subtractor example: dip

42、-switch based dip-switch based adding/subtracting calculatoradding/subtracting calculatordip switches108-bit registercalcledsefclkld88800888882x10110wiciaabbsscowo8-bit adder8-bit subtractor494949incrementerincrementeradds 1 to input as20001111000011110s10110011001100110s01010101010101010s3000000011

43、1111110c00000000000000001a00101010101010101a10011001100110011a30000000011111111inputsoutputsa200001111000011110 0 1 10 1 11+carries:unused00001505050incrementerincrementer(a)(b)a3a2a1a01s0s1s2s3coabcoshaabcoshaabcoshaabcoshaincrementer (+1)a3co s3s2+1s1 s0a2 a1 a0could design using combinational des

44、ign process, but smaller design uses carry-ripple, only need half-adders515151multiplier multiplier array style array stylecan build multiplier that mimics multiplication by handnotice that multiplying multiplicand by 1 is same as anding with 14.5525252multiplier multiplier array style array stylege

45、neralized representation of multiplication by hand535353multiplier multiplier array style array stylemultiplier design array of and gatesabp*block symbol+ (5-bit)+ (6-bit)+ (7-bit)000000a0a1a2a3b0b1b2b30p7.p0pp1pp2pp3pp454546.10.6 msi arithmetic and logic units 6.10.6 msi arithmetic and logic units

46、(alu, msi (alu, msi 算术逻辑单元算术逻辑单元) )perform any of a number of different arithmetic and logical operations on a pair of b-bit operands.( (对对2 2个个b b位的操作数进行若干不同的算术和逻辑运算位的操作数进行若干不同的算术和逻辑运算) )s0s3mcina0a3b0b3gpf0f3couta=b74x181输入数据输入数据输出数据输出数据0 0算术算术/1 1逻辑逻辑选择特定操作选择特定操作table 6-70table 6-70figure 6-90fig

47、ure 6-90 6-91 6-92 6-91 6-92 6-93 6-93digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )555555arithmetic-logic unit: aluarithmetic-logic unit: alualu: component that can perform various arithmetic (add, subtract, increment, etc.) and logic (and, or, etc.) operations, based on control inpu

48、ts 4.7565656arithmetic-logic unit: aluarithmetic-logic unit: alu4.75757multifunction calculator without an multifunction calculator without an alualucan build using separate components for each operation, and muxestoo many wires, also wastes power computing operations when only use one result at giv

49、en time5858multifunction calculator without an multifunction calculator without an alualudip switches108-bit register8-bit 8x1calcledsezyxclkids0s1s21 001 2 3 4 5 6 7notxororand+1+888888888888aba lot of wireswastedpower 595959alualumore efficient design uses alualu design not just separate component

50、s multiplexed (same problem as previous slide) instead, alu design uses single adder, plus logic in front of adders a and b inputslogic in front is called an arithmetic-logic extenderextender modifies a and b inputs so desired operation appears at output of the adder 6060alualu(a)aluiaibisaddercinab

51、sxyzal-extenderabextabextabext cinextal-extenderia7ib7a7b7ia6ib6a6b6ia0ib0a0b0cin(b)xyz616161arithmetic-logic extender in front of arithmetic-logic extender in front of alualuabextabextabextcinextxyzal-extenderia7 ib7a7 b7ia6 ib6a6 b6ia0 ib0a0 b0cin(b)(a)aluiaibisadder cinabal-extendersxyz626262arit

52、hmetic-logic extender in front of arithmetic-logic extender in front of alualuxyz=000 want s=a+b : just pass a to ia, b to ib, and set cin=0 xyz=001 want s=a-b : pass a to ia, b to ib and set cin=1 (twos complement)xyz=010 want s=a+1 : pass a to ia, set ib=0, and set cin=1xyz=011 want s=a : pass a t

53、o ia, set ib=0, and set cin=0 xyz=100 want s=a and b : set ia=a*b, b=0, and cin=0others: likewisebased on above, create logic for ia(x,y,z,a,b) and ib(x,y,z,a,b) for each abext, and create logic for cin(x,y,z), to complete design of the al-extender component6363alu example: multifunction alu example

54、: multifunction calculatorcalculatordip switches108-bit register8-bit 8x1calcledsezyxclkids0s1s21 001 2 3 4 5 6 7notxororand+1+888888888888aba lot of wireswastedpower 6464alu example: multifunction alu example: multifunction calculatorcalculatordesign using alu is elegant and efficientno mass of wir

55、esno big waste of powerdip switches10108-bit registeraluscalcledsezyxclkldzyx8888aabb6565s1 s0 y0 00 11 01 1aba+ba ba功能表功能表设计函数发生器，其功能表如下：设计函数发生器，其功能表如下：s1 s0 a b y0 0 0 00 0 0 1真值表真值表1 1、填写真值表、填写真值表2 2、选择器件、选择器件 用基本门电路实现用基本门电路实现 利用卡诺图化简利用卡诺图化简 用译码器实现用译码器实现 转换为最小项之和转换为最小项之和 用数据选择器实现用数据选择器实现3 3、电路处理、

56、电路处理注意有效电平注意有效电平digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )6666组合逻辑部分小结组合逻辑部分小结第第4 4章章 组合逻辑设计原理组合逻辑设计原理第第6 6章章 组合逻辑设计实践组合逻辑设计实践digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )6767第第4 4章章 基本原理基本原理 开关代数基础开关代数基础组合逻辑的基本分析、综合方法组合逻辑的基本分析、综合方法冒险冒险 开关代数的公理、定理开关代数的公理、定理 对偶、反演规则

57、对偶、反演规则 逻辑函数的表示法逻辑函数的表示法 分析步骤，利用公式进行化简分析步骤，利用公式进行化简 设计方法、步骤设计方法、步骤 利用卡诺图化简，电路处理利用卡诺图化简，电路处理 无关项的化简、多输出函数的化简无关项的化简、多输出函数的化简 冒险的检查和消除冒险的检查和消除digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )6868组合电路的分析组合电路的分析分析的目的：分析的目的：确定给定电路的逻辑功能确定给定电路的逻辑功能分析步骤：分析步骤：由输入到输出逐级写出逻辑函数表达式由输入到输出逐级写出逻辑函数表达式对输出逻

58、辑函数表达式进行化简对输出逻辑函数表达式进行化简判断逻辑功能（列真值表或画波形图）判断逻辑功能（列真值表或画波形图）digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )6969分析图示逻辑电路的功能分析图示逻辑电路的功能b3b2b1b0g3g2g1g0解：解：1、写表达式、写表达式2、列真值表、列真值表3、分析功能、分析功能0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1

59、1 01 1 1 1b3 b2 b1 b0g3 g2 g1 g00 0 0 00 0 0 10 0 1 1g3 = b3g2 = b3 b2g1 = b2 b1g0 = b1 b0二进制码至格雷码的转换电路二进制码至格雷码的转换电路0 0 1 00 1 1 00 1 1 10 1 0 10 1 0 01 1 0 01 1 0 11 1 1 11 1 1 01 0 1 01 0 1 11 0 0 11 0 0 0digital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )7070组合电路的综合组合电路的综合问题问题描述描述逻辑逻辑抽象

60、抽象选定选定器件器件类型类型函数化简函数化简电路处理电路处理将函数将函数式变换式变换电路电路实现实现真值表真值表或或函数式函数式用门电路用门电路用用msimsi组合组合电路或电路或pldplddigital logic design and application ( (数字逻辑设计及应用数字逻辑设计及应用) )71710 00 00 00 00 10 10 10 11 01 01 01 01 11 11 11 10 00 11 01 10 00 11 01 10 00 11 01 10 00 11 01 1x1 x0y1 y00 0 0 00 0 0 00 0 0 00 0 0 00 0 0