第四讲DSP外设应用之系统时钟

1、第四讲 DSP外设应用之系统时钟 系统时钟，即为各个模块产生所需要的时钟，如C55x core、慢速外设（Slow Peripherals），快速外设（Fast Peripherals）以及其它外设所需的基准时钟。系统时钟的设置是任何一个可编程器件必须进行的初始化操作。 在DSP5502中，系统的时钟初始化语句为：PLL_setFreq(1, 0xC, 0, 1, 3, 3, 0);该语句为CSL（Chip Support Library）库函数语句，在进行时钟设置时，系统调用该API初始化函数，以完成系统设置，对于C55x 5502所涉及的时钟寄存器如下表所示：系统涉及的函数原型为void

2、PLL_setFreq (Uint16 mode, Uint16 mul, Uint16 div0, Uint16 div1, Uint16 div2,Uint16 div3, Uint16 oscdiv);Uint16 mode / PLL mode /PLL_PLLCSR_PLLEN_BYP ASS_MODE /PLL_PLLCSR_PLLEN_PLL_MODEUint16 mul / Multiply factor, Valid values are (multiply by) 2 to 15.Uint16 div0 / Sysclk 0 Divide Down, Valid value

3、s are 0, (divide by 1) /to 31 (divide by 32)Uint16 div1 / Sysclk1 Divider, Valid values are 0, 1, and 3 corresponding/to divide by 1, 2, and 4 respectivelyUint16 div2 / Sysclk2 Divider, Valid values are 0, 1, and 3 /corresponding to divide by 1, 2, and 4 respectivelyUint16 div3 / Sysclk3 Divider, Va

4、lid values are 0, 1 and 3 /corresponding to divide by 1, 2 and 4 respectivelyUint16 oscdiv / CLKOUT3(DSP core clock) divider,Valid values are 0 /(divide by 1) to 31 (divide by 32)程序中，对于MODE,则5502有两种模式：PLL旁路模式和PLL使能模式，前者是时钟未经PLL进行倍频，而后者使用PLL功能。由于目前无源晶振生产工艺限制，其所能产生的频率超过30即会有较大的误差，而5502最高可达到300M时钟，一般需要

5、使能PLL功能。其它参数均为各除法器的值，查询相应的寄存器即可完成。表1 所涉及的PLL寄存器及其各相关位PLLCSR PLLEN, PLLPWRDN, OSCPWRDN, PLLRST, LOCK, STABLEPLLM PLLMPLLDIV0 PLLDIV0, D0ENPLLDIV1 PLLDIV1, D1ENPLLDIV2 PLLDIV2, D2ENPLLDIV3 PLLDIV3, D3ENOSCDIV1 OSCDIV1, OD1ENWAKEUP WKEN0, WKEN1, WKEN2, WKEN3CLKMD CLKMD0CLKOUTSRCLKOUTDIS, CLKOSEL图1 系统时钟

6、发生器图2 晶振及其时钟产生电路图3 内部时钟频率范围值图4 时钟发生器寄存器附各个寄存器相关位说明(1) PLL Control / Status Register (PLLCSR) (0x1c80)nSTABLE6R1Oscillator output stable. This bit indicates if the OSCOUT output has stabilized. STABLE = 0: Oscillator output is not yet stable. Oscillator counter is not done counting 41,032 reference c

7、lock cycles.STABLE = 1: Oscillator output is stable. This is true if any one of the three cases is true:a) Oscillator counter has finished counting.b) Oscillator counter is disabled.c) Test mode.LOCK5R0Lock mode indicator. This bit indicates whether the clock generator is in its lock mode.LOCK = 0:

8、The PLL is in the process of getting a phase lock.LOCK = 1: The clock generator is in the lock mode. The PLL has a phase lock and the output clock of the PLL has the frequency determined by the PLLM register and PLLDIV0 register.PLLRST3R/W1Asserts RESET to PLLPLLRST = 0: PLL reset releasedPLLRST = 1

9、: PLL reset assertedOSCPWRDN2R/W0Sets internal oscillator to power-down modeOSCPWRDN = 0: Oscillator operationalOSCPWRDN = 1: Oscillator set to power-down mode based onstate of CLKMD0 bit of Clock Mode Control Register (CLKMD).When CLKMD0 = 0, the internal oscillator is set to power-down mode when t

10、he clock generator is set to its idle mode CLKIS bit of the IDLE Status Register (ISTR) becomes 1.When CLKMD0 = 1, the internal oscillator is set to power-down mode immediately after the OSCPWRDN bit is set to 1.PLLPWRDN1R/W0Selects PLL power downPLLPWRDN = 0: PLL operational PLLPWRDN = 1: PLL place

11、d in power-down statePLLEN0R/W0PLL mode enable. This bit controls the multiplexer before dividers D1, D2, and D3.PLLEN = 0: Bypass mode. Divider D1 and PLL are bypassed. SYSCLK1 to 3 divided downdirectly from input reference clock. PLLEN = 1: PLL mode. Divider D1 and PLL are not bypassed. SYSCLK1 to

12、 3 divided down from PLL output.(2) PLL Multiplier Control Register (PLLM)15-54-0ReservedPLLMPLLM4:0R/W00000PLL multiplier-selectPLLM = 0000000001: ReservedPLLM = 00010: Times 2PLLM = 00011: Times 3PLLM = 00100: Times 4PLLM = 00101: Times 5PLLM = 00110: Times 6PLLM = 00111: Times 7PLLM = 01000: Time

13、s 8PLLM = 01001: Times 9PLLM = 01010: Times 10PLLM = 01011: Times 11PLLM = 01100: Times 12PLLM = 01101: Times 13PLLM = 01110: Times 14PLLM = 01111: Times 15PLLM = 1000011111: Reserved(3) PLL Divider 0 Register (PLLDIV0) (Prescaler)1514-54-0D0ENReservedPLLDIV0D0EN15R/W1Divider D0 enableD0EN = 0: Divi

14、der 0 disabledD0EN = 1: Divider 0 enabledPLLDIV04:0R/W00000Divider D0 ratioPLLDIV0 = 00000: Divide by 1PLLDIV0 = 00001: Divide by 2PLLDIV0 = 00010: Divide by 3.PLLDIV0 = 11111: Divide by 32(4)PLL Divider1 Register (PLLDIV1) for SYSCLK11514-54-0D1ENReservedPLLDIV1D1EN15R/W1Divider D1 enableD1EN = 0:

15、Divider 1 disabledD1EN = 1: Divider 1 enabledPLLDIV14:0R/W00011Divider D1 ratio (SYSCLK1 divider)PLLDIV1 = 00000: Divide by 1PLLDIV1 = 00001: Divide by 2PLLDIV1 = 00010: ReservedPLLDIV1 = 00011: Divide by 4PLLDIV1 = 0010011111: ReservedPLLDIV2和PLLDIV3的位定义与PLLDIV1完全一样，在此不再重复写了。(5) Oscillator Divider1

16、 Register (OSCDIV1) for CLKOUT31514-54-0OD1ENReservedOSCDIV1OD1EN15R/W0Divider D0 enableD0EN = 0: Divider 0 disabledD0EN = 1: Divider 0 enabledOSCDIV14:0R/W00000Divider D0 ratioPLLDIV0 = 00000: Divide by 1PLLDIV0 = 00001: Divide by 2PLLDIV0 = 00010: Divide by 3.PLLDIV0 = 11111: Divide by 32(6) CLKOUT3 Select Register (CK3SEL)15-43-0ReservedCK3SELCK3SEL3:0R/W1011Output on C