Verilog语言描述常见电路结构范例

1、Verilog 语言描述常见电路结构范例组合逻辑常见的组合逻辑有 :算术逻辑部件、多路选择器、编码器、优先编码器、译码器和比较器等。逻辑结构控制使用括号可以改变组合逻辑的结构。虽然 EDA 工具可以对组合逻辑设计进行重新优化组合 ,但在 Verilog 描述中使用括号可以降低 EDA 工具的压力 ,并且减少工具的综合时间。在下面的例子中 ,虽然 y2 和 y1 的功能是一样的 ,但 y1 会使用三级加法器 ,使用括号的 y2 只使用二级加法器。always (a1 or a2 or b1 or b2 or c1 or c2 or d1 or d2 beginy1 = a1 + b1 + c1

2、+ d1;y2 = (a2 + b2 + (c2 + d2;end二选一多路选择器下面给出了三种描述2:1 MUX 的方法。 y1 是通过条件赋值语句实现的,y2 和y3 都是通过 if 语句实现的。wire y1 = sel1? a1: b1;always (a2 or a3 or b2 or b3 or sel2 or sel3 beginy2 = b2;if (sel2 y2 = a2;if (sel3 y3 = a3;else y3 = b3;end四选一多路选择器用 Verilog 描述 4:1 MUX 可以有如下方法 :一个 if 语句加多个 else if 从句嵌套 if 语句c

3、ase语句always (a or b or c or d or sel beginif (sel = 2b00 y = a;else if (sel = 2b01 y = b;else if (sel = 2b10 y = c;else y = d;endalways (a or b or c or d or sel beginif (sel1 = 0if (sel0 = 0 y = a;else y = b;elseif (sel0 = 0 y = c;else y = d;endalways ( a or b or c or d or sel begincase (sel2b00: y

4、= a;2b01: y = b;2b10: y = c;2b11: y = d;default: y = a;endcaseend八选一多路选择器描述 8:1 MUX 最好使用 case语句always ( a0 or a1 or a2 or a3 or a4 or a5 or a6 or a7 or sel begincase (sel0: y = a0;1: y = a1;2: y = a2;3: y = a3;4: y = a4;5: y = a5;6: y = a6;7: y = a7; default: y = a0;endcaseend8:3 编码器编码器可以将多个离散的信号用编码

5、表示出来,比如 3 位的编码可以表示8 个信号。下面的例子给出了三种8:3 编码器的描述方法。always (a beginif (a = 8b00000001 y = 0;else if (a = 8b00000010 y = 1;else if (a = 8b00000100 y = 2;else if (a = 8b00001000 y = 3;else if (a = 8b00010000 y = 4;else if (a = 8b00100000 y = 5;else if (a = 8b01000000 y = 6;else if (a = 8b10000000 y = 7;els

6、e y = 3bX;endalways (a begincase (a8b00000001: y = 0;8b00000010: y = 1;8b00000100: y = 2;8b00001000: y = 3;8b00010000: y = 4;8b00100000: y = 5;8b01000000: y = 6;8b10000000: y = 7;default: y = 3bX;endcaseendalways ( a begintest = 8b00000001;y = 3bX;for (i=0; i8; i=i+1 beginif ( a = testy = i;test = t

7、est 1;endend优先级编码器优先级编码器是一种特殊的编码器,就是当多个输入信号同时有效时,它只输出优先级最高的信号的编码。下面的例子给出了8:3 优先级编译器的描述方法。always (a beginvalid = 1;if (a7 y = 7;else if (a6 y = 6;else if (a5 y = 5;else if (a4 y = 4;else if (a3 y = 3;else if (a2 y = 2;else if (a1 y = 1;else if (a0 y = 0;else beginvalid = 0;y = 3bx;endendalways (a beg

8、invalid = 1;casez(a8b1?: y = 7;8b01?: y = 6;8b001?: y = 5;8b0001?: y = 4;8b00001?: y = 3;8b000001?: y = 2;8b0000001?: y = 1;8b00000001: y = 0;default: beginvalid = 0;y = 3bx;endendcaseendalways ( a or n beginvalid = 0;y = 3bx;for (i=8; i8; i=i+1 beginif (ai beginvalid = 1;y = i;endendend译码器译码器的作用恰好与

9、编码器相反,它从编好的码中把原始信号还原出来。下面的例子给出了三种3:8 译码器的描述方法 :always (a beginif (a = 0 y = 8b00000001;else if (a = 1 y = 8b00000010;else if (a = 2 y = 8b00000100;else if (a = 3 y = 8b00001000;else if (a = 4 y = 8b00010000;else if (a = 5 y = 8b00100000;else if (a = 6 y = 8b01000000;else y = 8b10000000;endalways (a

10、begincase (a0: y = 8b00000001;1: y = 8b00000010;2: y = 8b00000100;3: y = 8b00001000;4: y = 8b00010000;5: y = 8b00100000;6: y = 8b01000000;7: y = 8b10000000; default: y = 8bX;endcaseendalways (a or n beginfor (i=0; i8; i=i+1 beginif ( a = n yi = 1;else yi = 0;endend比较器比较器用于比较两个或多个输入的关系,如相等、不等、大小等。下面的

11、例子给出了三种 6 位比较器的描述方法。always ( a1 or a2 or a3 or b1 or b2 or b3 beginy1 = 1;for (n=0; n6; n=n+1if (a1n != b1n y1 = 0;y2 = 0;if (a2 = b2 y2 = 1;if (a3 = b3 y3 = 1;else y3 = 0;end时序逻辑 时序逻辑包括 latch、触发器、计数器等， latch 产生的主要原因是 if 或 case语句中的条件不完整，这是要 努力避免的。 D 触发器 always (posedge clk begin if (!rst_syn y1 = 0;

12、 else y1 = d1; end always (posedge clk or negedge rst_n begin if (!rst_n y2 = 0; else y2 = d2; end always (posedge clk or negedge rst_n begin if (!rst_n y3 = 0; else if (rst_syn y3 = 0; else y3 = d3; end always (posedge clk if (en y4 = d4; always (posedge clk if (rst_syn y5 = 0; else if (en y5 = d5;

13、 always (posedge clk or negedge rst_n if (rst_n y6 = 0; else if (en y6 = d6;计数器 always ( posedge clk or negedge rst_n begin if (!rst_n counter = 0; else begin case(up,down 2b10: counter = counter + 1; 2b01: counter = counter - 1; endcase end end有限状态机 FSM 由状态寄存器、下一状态逻辑和输出逻辑组成。下面的例子给出了一个 FSM 的描述方法。 mo

14、dule fsm1 (ds, rd, go, ws, clk, rst_n; output ds, rd;input go, ws; input clk, rst_n; reg ds, rd; parameter 1:0 IDLE = 2b00, READ = 2b01,DLY = 2b10, DONE = 2b11; reg 1:0 state, next; always (posedge clk or negedgerst_n if (!rst_n state = IDLE; else state = next; always (state or go or ws begin next =2bx; ds = 1b0; rd